公开(公告)号：US07401319B2

公开(公告)日：2008-07-15

申请号：US11021783

申请日：2004-12-23

申请人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

发明人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

摘要： A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

摘要翻译： 分层表示使用单元定义（CellDef）的概念来封装子电路的详细内部组成。 CellDef作为操作重用的自然单元。 如果基于CellDef或一个单元实例的分析或操作所需的计算（例如寄生提取，RET，设计规则确认（DRC）或OPC））可以无需或最小的额外努力应用于所有或重要的 单元的其他实例的子集可以实现计算量的非常大的减少。 此外，分层表示还允许将整个分析/操作任务划分成子任务的集合，例如子集。 每个CellDef一个。 然后可以将多个作业分布在网络上的大量计算节点上以用于并发执行。 虽然这可能不会减少总体计算时间，但总体周转时间（TAT）的大幅减少本身就是非常有益的。

公开(公告)号：US5790048A

公开(公告)日：1998-08-04

申请号：US961545

申请日：1997-10-30

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00 ,  G06F13/00

CPC分类号： H03K19/1736

摘要： A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

摘要翻译： 交叉点交换机通过从主机控制器的路由数据定义的路由模式在其终端之间路由信号。 交叉点开关包括传输晶体管阵列。 每个通过晶体管在导通时提供一个信号路径，互连独立的一对开关端子。 交叉点开关还包括两个静态随机存取存储体。 每个存储体存储定义单独路由模式的路由数据，并产生反映其存储的数据的单独的一组输出信号。 多路复用器将所选择的一个存储器组的输出信号传送到开关阵列，以控制其传输晶体管，使得开关阵列实现由所选存储体中的数据定义的布线图案。 通过将定义不同路由模式的路由数据加载到两个存储体中，主控制器随后可以通过切换多路复用器的控制输入来快速地使交叉点开关交替在两个路由模式之间。

公开(公告)号：US07444615B2

公开(公告)日：2008-10-28

申请号：US11139551

申请日：2005-05-31

申请人： Gokhan Percin ,  Ram S. Ramanujam ,  Franz X. Zach ,  Abdurrahman Sezginer ,  Chi-Song Horng ,  Roy Prasad

发明人： Gokhan Percin ,  Ram S. Ramanujam ,  Franz X. Zach ,  Abdurrahman Sezginer ,  Chi-Song Horng ,  Roy Prasad

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F1/44 ,  G03F1/68

摘要： A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.

摘要翻译： 提供了一种产生OPC模型的方法，其考虑了在制造半导体芯片的过程中发生的跨晶片变化。 更具体地，提供了一种用于生成OPC模型的方法，其考虑了在基于在“晶片甜点”处测量的测试图案的参数的制造半导体芯片的过程期间发生的跨晶片变化，以便到达 准确模型。

公开(公告)号：US06738788B1

公开(公告)日：2004-05-18

申请号：US10124860

申请日：2002-04-17

申请人： Chi-Song Horng ,  Keith Lofstrom

发明人： Chi-Song Horng ,  Keith Lofstrom

IPC分类号： G06F1730

CPC分类号： G06F17/30286 ,  Y10S707/99942 ,  Y10S707/99945

摘要： A database system accesses database records referenced by a binary number key having two fields, a typeID field containing only deterministic bits, and a uniqueID field permissibly containing one or more non-deterministic bits at any bit positions therein. The database system maintains a set of databases, each being identified by a separate value of the typeID field of the binary number key. The records of each database are allocated among a plurality of bins, with each bin being identified (keyed) by separate value of a binID field, and with each record being identified (keyed) by a separate value of a recID field. The database system locates a record of interest referenced by the binary number key by first selecting a particular one of the databases that is identified by the typeID field of the binary number key. It then compares a portion of selected bits of the binary number key's uniqueID field to binID values identifying bins of the selected database to determine a subset of the bins that may include the record of interest. The database system then compares the full uniqueID field of the binary number key to the recIDs values for records of the subset of bins to determine which particular recID field identifies the record of interest.

摘要翻译： 数据库系统访问由具有两个字段的二进制数字键引用的数据库记录，仅包含确定性位的typeID字段以及在其中的任何位位置允许包含一个或多个非确定性位的唯一ID字段。 数据库系统维护一组数据库，每个数据库由二进制数字键的typeID字段的单独值标识。 每个数据库的记录被分配在多个箱之间，其中每个仓被binID字段的分开的值识别（加密），并且每个记录由recID字段的单独的值标识（加密）。 数据库系统通过首先选择由二进制数字键的typeID字段标识的特定数据库来定位由二进制数字键引用的感兴趣的记录。 然后，它将二进制数密钥的唯一ID字段的所选位的一部分与识别所选数据库的存储区的binID值进行比较，以确定可能包括感兴趣的记录的仓的子集。 数据库系统然后将二进制数字键的完整uniqueID字段与bin的子集的记录的recIDs值进行比较，以确定哪个特定的recID字段标识感兴趣的记录。

公开(公告)号：US5710550A

公开(公告)日：1998-01-20

申请号：US516322

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

IPC分类号： G06F15/173 ,  H04Q11/04 ,  H03K17/0412

CPC分类号： G06F15/17375 ,  H04Q11/0478

摘要： A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.

摘要翻译： 现场可编程互连设备（FPID）响应于来自主机控制器的命令，有选择地在信号端口之间路由信号。 每个命令包括地址和数据。 FPID包括开关单元阵列，每个开关单元互连一个单独的端口对，并且每个具有第一和第二控制信号输入。 当第一和第二控制信号均被断言时，开关单元在其互连的一对端口之间提供信号路径。 FPID包括用于存储数据的第一和第二组存储器单元。 每个第一存储器单元对应于开关单元中的单独单元，并根据其存储的数据选择性地断言或解除输入到相应开关单元的第一控制信号。 每个第二存储器单元对应于单独的开关单元组，并根据其存储的数据选择性地断言或解除输入到相应组的每个开关单元的第二控制信号。 FPID还包括存储器控制器，用于从主机控制器接收每个命令，并且用于在接收到命令时将包括在命令中的数据写入第一和第二存储器单元的特定子集的每个存储单元。 命令中包含的地址表示控制器写入数据的特定子集。 包含在特定子集中的存储单元的数量是地址的可变函数。

公开(公告)号：US5530814A

公开(公告)日：1996-06-25

申请号：US333290

申请日：1994-11-02

申请人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： G06F13/36 ,  G06F15/173 ,  H03K19/173 ,  H03K19/177 ,  H05K1/00 ,  G06F13/00

CPC分类号： G06F15/17375 ,  H03K19/1736 ,  H03K19/17704 ,  H05K1/0286

摘要： A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

摘要翻译： 分层交叉开关包括几个开关阵列，每个开关阵列包括几个开关单元。 每个开关单元互连一个唯一的一对信号端口，并且在通过使能信号接通时在互连的信号端口之间提供双向信号路径。 第一存储器阵列存储指示要接通的特定开关单元的输入数据。 第二存储器阵列存储指示要启用的特定开关阵列的输入数据。 交叉开关还包括逻辑单元阵列，其读取存储在第一和第二存储器中的数据，并向每个开关单元发送单独的控制信号。 当第一和第二存储器阵列中的数据指示要切换开关单元并且包括开关单元的开关单元阵列将被启用时，每个控制信号切换其所发送的开关单元。

公开(公告)号：US5428750A

公开(公告)日：1995-06-27

申请号：US171751

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F13/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable logic module provides a set of sockets for mounting electronic components, a set of connector pins for providing external access to the board, and a set of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports can be programmed to provide various types of buffering and logic operations on the signals routed by the FPIDs.

摘要翻译： 现场可编程逻辑模块提供一组插座，用于安装电子元件，一组连接器引脚，用于提供对板的外部访问，以及一组现场可编程互连设备（FPID）。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口中的信号缓冲器可以编程为对FPID路由的信号提供各种类型的缓冲和逻辑运算。

公开(公告)号：US5426738A

公开(公告)日：1995-06-20

申请号：US171752

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F3/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

摘要翻译： 现场可编程电路板提供一组用于接收电子元件的插座，一组连接器引脚，用于提供对板的外部访问以及现场可编程互连器件（FPID）阵列。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口内的信号缓冲区会自动检测由FPID路由的双向信号的流向，并按适当的方向缓冲信号。 每个FPID缓冲器还在几个系统时钟周期上采样和存储指示缓冲信号状态的数据，以供主计算机随后读出。

公开(公告)号：US5734334A

公开(公告)日：1998-03-31

申请号：US516320

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00

CPC分类号： H03K19/1736

摘要： An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由数字和模拟信号。 每个端子的独立端口为数字和模拟信号流入和流出交换机提供了路径。 每个端口可被配置为在三态控制信号的控制下具有或不具有三态缓冲器，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及缓冲通过或者流过开关端子的信号， 没有输入方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。

公开(公告)号：US5717871A

公开(公告)日：1998-02-10

申请号：US516319

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： G06F13/40 ,  H04L12/56 ,  H04Q3/68 ,  G06F3/00

CPC分类号： G06F13/4022 ,  H04L49/25 ,  H04Q3/68 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13106 ,  H04Q2213/13141 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller. Each port stores an internal port address and when the key address matches the port address, the port asserts an internal "KEY" signal. Each port may be configured to use the KEY signal selectively as either its tristate, clock enable, clock or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由信号。 为每个端子提供的单独端口缓冲流入和流出开关的信号。 每个端口可以被配置为在三态控制信号的控制下操作有或没有三态缓冲，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及响应于缓冲转换到终端的信号 到方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。 还向所有端口提供并行“键”总线，用于从主机控制器传送密钥地址。 每个端口存储内部端口地址，当密钥地址与端口地址匹配时，端口置位一个内部“KEY”信号。 每个端口可以被配置为选择性地使用KEY信号作为其三态，时钟使能，时钟或方向控制信号。