公开(公告)号：US06780724B2

公开(公告)日：2004-08-24

申请号：US10069893

申请日：2002-02-27

申请人： Doede Terpstra ,  Catharina Huberta Henrica Emons

发明人： Doede Terpstra ,  Catharina Huberta Henrica Emons

IPC分类号： H01L218222

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： The invention relates to a method of manufacturing implanted-base, double polysilicon bipolar transistors whose emitter, base and collector are all situated in a single active area. In accordance with the method, first the island isolation (3) defining the active area (4) in the silicon body (1) is provided, which active area forms the collector (5). A first polysilicon layer (6) is deposited on the surface. A first part (6a) of poly I is p-type doped, a second part is n-type doped. By etching, two separate parts are formed from the first poly layer, one part being p-type doped and forming a base terminal (8), the other part being n-type doped and forming a collector terminal (9), said two parts being separated by an intermediate region (16) where the surface of the active area is exposed. The edges of these poly terminals and the exposed parts of the active area are provided with spacers (13, 15) and spacers (14, 16), respectively. After the provision of the intrinsic base region (11), a non-walled emitter (19) and the emitter terminal (18) in the form of an n-type doped second poly layer are provided in said intermediate region between the base and collector-terminals.

摘要翻译： 本发明涉及一种制造植入式双重多晶硅双极晶体管的方法，其发射极，基极和集电极都位于单个有源区域中。 根据该方法，首先提供在硅体（1）中限定有源区（4）的岛隔离（3），该有效区形成集电极（5）。 第一多晶硅层（6）沉积在表面上。 聚I的第一部分（6a）是p型掺杂的，第二部分是n型掺杂的。 通过蚀刻，从第一多晶硅层形成两个分开的部分，一部分是p型掺杂并形成基极（8），另一部分是n型掺杂并形成集电极端子（9），所述两个部分 由其中暴露有源区域的表面的中间区域（16）分离。 这些多晶硅端子的边缘和有源区域的露出部分分别设置有间隔物（13,15）和间隔物（14,16）。 在提供本征基极区域（11）之后，在基极和集电极之间的所述中间区域中设置非壁发射极（19）和n型掺杂的第二多晶硅层形式的发射极端子（18） - 终结者

公开(公告)号：US06410395B1

公开(公告)日：2002-06-25

申请号：US09713865

申请日：2000-11-16

申请人： Doede Terpstra ,  Jan Willem Slotboom ,  Youri Ponomarev ,  Petrus Hubertus Cornelis Magnee ,  Freerk Van Rijs

发明人： Doede Terpstra ,  Jan Willem Slotboom ,  Youri Ponomarev ,  Petrus Hubertus Cornelis Magnee ,  Freerk Van Rijs

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L27/0826

摘要： A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.

摘要翻译： 一种制造包括异质结双极晶体管（HBT）的半导体器件的方法，其中单晶硅的第一半导体层（5），第二半导体单晶硅的半导体层，包括5至25μm。 通过外延沉积，在硅晶片（1）的表面（2）上依次提供了锗（6）和单晶硅（7）的第三半导体层。 在第二半导体层中形成晶体管的基极区。 在该方法中，第二半导体层被沉积而不进行基底掺杂，所述掺杂在稍后阶段形成。 所述掺杂可以通过离子注入工艺或VPD（气相掺杂）工艺形成。 该方法使得能够制造包括npn晶体管的集成电路以及pnp晶体管。

公开(公告)号：US06368946B1

公开(公告)日：2002-04-09

申请号：US08822747

申请日：1997-03-24

申请人： Ronald Dekker ,  Cornelis E. Timmering ,  Doede Terpstra ,  Wiebe B. De Boer

发明人： Ronald Dekker ,  Cornelis E. Timmering ,  Doede Terpstra ,  Wiebe B. De Boer

IPC分类号： H01L21265

CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

摘要： A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a surface of a silicon wafer, a window with a steep wall is etched through the second layer of insulating material and the first layer of non-monocrystalline silicon, the wall of the window is provided with a protective layer, the first insulating layer is selectively etched away within the window and below an edge of the first layer of non-monocrystalline silicon adjoining the window such that both the edge of the first layer of non-monocrystalline silicon itself and the surface of the wafer become exposed within the window and below said edge, semiconductor material is selectively deposited such that the epitaxial semiconductor zone is formed on the exposed surface of the wafer, and an edge of polycrystalline semiconductor material connected to the epitaxial semiconductor zone is formed on the exposed edge of the first layer of non-monocrystalline silicon, an insulating spacer layer is provided on the proctective layer on the wall of the window, and a second layer of non-monocrystalline silicon is deposited. The provision of a top layer of a material on which non-monocrystalline semiconductor material will grow during the selective deposition of the semiconductor material, which top layer is provided on the second layer of insulating material before the selective deposition of the semiconductor material, achieves that the selective deposition process can be better monitored.

摘要翻译： 制造具有外延半导体区域的半导体器件的方法，其中第一绝缘材料层，第一非晶硅层和第二绝缘材料层依次设置在硅晶片的表面上， 通过绝缘材料的第二层和非单晶硅的第一层蚀刻具有陡峭壁的窗口，窗口的壁设置有保护层，第一绝缘层被选择性地蚀刻在窗口内并在窗口下方 邻接窗口的非单晶硅第一层的边缘使得第一层非单晶硅本身的边缘和晶片的表面两者都在窗口内部和所述边缘的下方露出，半导体材料被选择性地沉积如 外延半导体区形成在晶片的暴露表面上，并连接多晶半导体材料的边缘 在第一非晶硅单层的暴露边缘上形成外延半导体区，在窗口壁上的保护层上提供绝缘间隔层，并沉积第二层非单晶硅。 在选择性沉积半导体材料的选择性沉积期间，在半导体材料的选择性沉积之前，提供非单晶半导体材料将在其上生长的材料的顶层，该半导体材料在半导体材料的选择性沉积之前设置在第二绝缘材料层上， 可以更好地监测选择性沉积过程。

公开(公告)号：US06908804B2

公开(公告)日：2005-06-21

申请号：US10648870

申请日：2003-08-27

申请人： Hendrik Gezienus Albert Huizing ,  Jan Willem Slotboom ,  Doede Terpstra ,  Johan Hendrik Klootwijk ,  Eyup Aksen

发明人： Hendrik Gezienus Albert Huizing ,  Jan Willem Slotboom ,  Doede Terpstra ,  Johan Hendrik Klootwijk ,  Eyup Aksen

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L21/8238

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material.The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs.The invention also relates to a semiconductor device comprising such a bipolar transistor.The method of manufacturing the bipolar transistor comprises the step of forming an emitter region (3) with a first doping type on a collector region (1) of a semiconductor material with a first doping type, and a base region (2) of a semiconductor material having a second doping type. The emitter region (3) is formed by epitaxially depositing a first layer (6) of a first semiconductor material and subsequently epitaxially depositing a second layer (7) of a second semiconductor material. The second layer (7) is doped with the first doping type, such that Auger recombination occurs. The intrinsic carrier concentration of the second semiconductor material is higher than the intrinsic carrier concentration of the first semiconductor material.The Auger recombination dominates the base current and allows accurate tuning of the base current and the current gain of the bipolar transistor.

公开(公告)号：US06759696B2

公开(公告)日：2004-07-06

申请号：US10210499

申请日：2002-08-01

申请人： Hendrik Gezienus Albert Huizing ,  Jan Willem Slotboom ,  Doede Terpstra ,  Johan Hendrik Klootwijk ,  Eyup Aksen

发明人： Hendrik Gezienus Albert Huizing ,  Jan Willem Slotboom ,  Doede Terpstra ,  Johan Hendrik Klootwijk ,  Eyup Aksen

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material. The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs. The invention also relates to a semiconductor device comprising such a bipolar transistor. The method of manufacturing the bipolar transistor comprises the step of forming an emitter region (3) with a first doping type on a collector region (1) of a semiconductor material with a first doping type, and a base region (2) of a semiconductor material having a second doping type. The emitter region (3) is formed by epitaxially depositing a first layer (6) of a first semiconductor material and subsequently epitaxially depositing a second layer (7) of a second semiconductor material. The second layer (7) is doped with the first doping type, such that Auger recombination occurs. The intrinsic carrier concentration of the second semiconductor material is higher than the intrinsic carrier concentration of the first semiconductor material. The Auger recombination dominates the base current and allows accurate tuning of the base current and the current gain of the bipolar transistor.

摘要翻译： 双极晶体管包括具有第一掺杂类型的半导体材料的集电极区域（1），具有第二掺杂类型的半导体材料的基极区域（2）和具有第一掺杂类型的发射极区域（3）。 在发射极区域（3）和基极区域（2）之间存在结，并且从结（4）观察，耗尽区域（5）延伸到发射极区域（3）中。 发射极区域（3）包括第一半导体材料的层（6）和第二半导体材料的层（7）。第一半导体材料具有比第二半导体材料更高的本征载流子浓度。 所述第二半导体材料的层（7）位于耗尽区（5）的外部。 第二半导体材料具有发生俄歇复合的掺杂浓度。本发明还涉及包括这种双极晶体管的半导体器件。制造双极晶体管的方法包括以下步骤：形成具有第一掺杂的发射极区（3） 类型在具有第一掺杂类型的半导体材料的集电极区域（1）上，以及具有第二掺杂类型的半导体材料的基极区域（2）。 发射极区（3）通过外延地沉积第一半导体材料的第一层（6）并随后外延地沉积第二半导体材料的第二层（7）而形成。 第二层（7）掺杂有第一掺杂类型，使得发生俄歇复合。 第二半导体材料的本征载流子浓度高于第一半导体材料的本征载流子浓度。俄歇复合支配基极电流，并允许精确调谐双极晶体管的基极电流和电流增益。

公开(公告)号：US6150224A

公开(公告)日：2000-11-21

申请号：US393944

申请日：1999-09-10

申请人： Doede Terpstra ,  Catharina H. H. Emons

发明人： Doede Terpstra ,  Catharina H. H. Emons

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66287 ,  H01L29/66242

摘要： The invention relates to the manufacture of a so-called differential bipolar transistor comprising a base (1A), an emitter (2) and a collector (3), the base (1A) being formed by applying a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body (10) where it forms the (monocrystalline) base (1A), and which semiconducting layer (1) borders, outside said monocrystalline part, on a non-monocrystalline part (4, 8) of the semiconductor body (10) where it forms a (non-monocrystalline) connecting region (1B) of the base (1A). The non-monocrystalline part (4, 8) of the semiconductor body (10) is obtained by covering the semiconductor body (10) with a mask (20) and replacing on either side thereof a part (8) of the semiconductor body (10) by an electrically insulating region (8) and by providing this, prior to the application of the semiconducting layer (1) with a polycrystalline semiconducting layer (4). The known method, in which an aperture is etched above the collector (3) after deposition of the polycrystalline layer (4), is relatively laborious. In a method in accordance with the invention, the polycrystalline layer (4) is selectively provided on the electrically insulating region (8), in which process use is made of the mask (20) to form the electrically insulating region (8). This method is less laborious than the known method. In addition, the resultant transistors have excellent properties and their dimensions may be very small. Preferably, both in the manufacture of the insulating region (8), preferably an oxide-filled groove (8), and in the process of selectively applying the polycrystalline layer (4) to the insulating region, use is made of a deposition step followed by a chemico-mechanical polishing step.

摘要翻译： 本发明涉及一种所谓的差分双极型晶体管的制造，所述差分双极晶体管包括基极（1A），发射极（2）和集电极（3），所述基极（1A）通过施加掺杂的半导体层 局部地邻接在半导体本体（10）的单晶部分（3）上，其形成（单晶）基底（1A），并且该半导体层（1）在非单晶部分（4） ，8），其形成所述基座（1A）的（非单晶）连接区域（1B）。 半导体本体（10）的非单晶部分（8）通过用掩模（20）覆盖半导体本体（10）并在其任一侧替换半导体本体（10）的一部分（8） ），并且通过在将半导体层（1）施加到多晶半导体层（4）之前提供该绝缘区域（8）。 在沉积多晶层（4）之后，在集电体（3）上方蚀刻孔径的已知方法相当费力。 在根据本发明的方法中，多晶层（4）选择性地设置在电绝缘区域（8）上，其中使用掩模（20）来形成电绝缘区域（8）。 这种方法比已知方法费力。 此外，所得的晶体管具有优异的性能，其尺寸可能非常小。 优选地，在绝缘区域（8）的制造中，优选地是氧化物填充的凹槽（8），并且在将多晶层（4）选择性地施加到绝缘区域的过程中，使用随后的沉积步骤 通过化学机械抛光步骤。

公开(公告)号：US06100152A

公开(公告)日：2000-08-08

申请号：US387629

申请日：1999-08-31

申请人： Catharina H. H. Emons ,  Doede Terpstra ,  Cornelis E. Timmering ,  Wiebe B. De Boer

发明人： Catharina H. H. Emons ,  Doede Terpstra ,  Cornelis E. Timmering ,  Wiebe B. De Boer

IPC分类号： H01L21/22 ,  H01L21/223 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L27/082

CPC分类号： H01L29/66287 ,  H01L29/66242 ,  H01L21/223 ,  H01L21/2252

摘要： The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). Such a method surprisingly results in a much faster transistor. It has been found that this enables, on the one hand, a much smaller diffusion in the thickness direction of the doping of the base (1A) to be achieved, which results in a much faster transistor, particularly, if the base (1A) contains SiGe. On the other hand, the lateral diffusion from the connecting region (1B) to the base (1A) is particularly strongly suppressed. This too has a beneficial effect on the speed of the transistor. The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950.degree. C. for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850.degree. C.