公开(公告)号：US06744304B2

公开(公告)日：2004-06-01

申请号：US10234078

申请日：2002-09-03

申请人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

发明人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

IPC分类号： G05F322

CPC分类号： G05F3/225

摘要： An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

摘要翻译： 用于产生输出电压的电子电路具有确定的温度依赖性，用于产生限定的温度恒定电压的带隙电路和具有确定的温度依赖性的依赖于温度的电流，以及用于从温度依赖性产生输出电压的转换电路， 依赖电流和温度恒定电压。 转换电路具有第一电阻器，其第一端子施加温度恒定电压，并且其第二端子连接到第二电阻器的第一端子。 第二电阻器的第二端子连接到电源电压电位，第三电阻器的第一端子连接到第一电阻器的第二端子。 温度相关电流被提供给第三电阻器的第二端子，并且可以抽出第三电阻器的第二端子处的输出电压。

公开(公告)号：US07532523B2

公开(公告)日：2009-05-12

申请号：US11461380

申请日：2006-07-31

申请人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

发明人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G06F13/4086 ,  G11C5/04

摘要： Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

摘要翻译： 用于设置存储芯片的各种终端的方法和装置。 存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口以及连接到终端的控制电路 电路，以便根据接收到的控制命令信号设置电阻值。

公开(公告)号：US20060262613A1

公开(公告)日：2006-11-23

申请号：US11410320

申请日：2006-04-24

申请人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

发明人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.

摘要翻译： 提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入 数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。 该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

公开(公告)号：US07573741B2

公开(公告)日：2009-08-11

申请号：US11236970

申请日：2005-09-28

申请人： Andreas Jakobs ,  Eckehard Plaettner

发明人： Andreas Jakobs ,  Eckehard Plaettner

IPC分类号： G11C11/34

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/2254

摘要： The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences. The subject matter of the invention is also circuit arrangements for performing this method.

摘要翻译： 本发明描述了一种用于在存储器系统中调整信号传播时间的方法，其中控制器经由多个连接线连接到至少一个存储器芯片，用于发送控制和数据信号以及至少一个时间参考信号。 根据本发明，从回波测量的结果确定连接线之间的传播时间差。 为此，将相应的发送脉冲施加到所讨论的连接线的选择为发送端的一端，而所讨论的连接线的另一端分别以反射端接终止。 在发送端，测量从另一端反射的发送脉冲的一个边缘和该边缘的回波的出现之间经过的回波时间。 在确定的传播时间差的基础上，设定可调节延迟装置以补偿这些传播时间差。 本发明的主题也是用于执行该方法的电路装置。

公开(公告)号：US07457174B2

公开(公告)日：2008-11-25

申请号：US11410320

申请日：2006-04-24

申请人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

发明人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.

摘要翻译： 提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入 数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。 该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

公开(公告)号：US20070035326A1

公开(公告)日：2007-02-15

申请号：US11461380

申请日：2006-07-31

申请人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

发明人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

IPC分类号： H03K19/003

CPC分类号： G11C7/1048 ,  G06F13/4086 ,  G11C5/04

摘要： Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

摘要翻译： 用于设置存储芯片的各种终端的方法和装置。 在一个实施例中，存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口，以及控制电路， 连接到终端电路，以便根据接收到的控制命令信号设置电阻值。

公开(公告)号：US20060109869A1

公开(公告)日：2006-05-25

申请号：US11236970

申请日：2005-09-28

申请人： Andreas Jakobs ,  Eckehard Plaettner

发明人： Andreas Jakobs ,  Eckehard Plaettner

IPC分类号： H04J3/06

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/2254

摘要： The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences. The subject matter of the invention is also circuit arrangements for performing this method.

公开(公告)号：US06762630B2

公开(公告)日：2004-07-13

申请号：US10033123

申请日：2001-10-22

申请人： Heiko Fibranz ,  Eckehard Plaettner

发明人： Heiko Fibranz ,  Eckehard Plaettner

IPC分类号： H03L700

CPC分类号： G11C7/1006 ,  G11C2207/104 ,  H03K5/135

摘要： An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

摘要翻译： 集成电路具有同步电路和异步电路。 时钟控制输入寄存器电路和用于存储数据的输出寄存器电路各自连接到同步电路和异步电路。 数据从同步电路传送到输入寄存器电路，从它们被传送到异步电路并在异步电路中进行处理。 处理的数据被传送到输出寄存器电路。 序列控制器以取决于异步电路的数据处理持续时间的方式为寄存器电路产生相应的控制时钟信号。 这使得独立于同步电路的时钟频率的同步电路和异步电路之间的高数据吞吐量。