公开(公告)号：US20060179334A1

公开(公告)日：2006-08-10

申请号：US11054392

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

发明人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在用于操作DIMM和/或DRAM的预定/预设阈值功率/温度值以上的热点。 存储器控制器逻辑基于从特定DIMM / DRAM接收的反馈数据达到预设阈值功率使用值，来限制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20080091906A1

公开(公告)日：2008-04-17

申请号：US11951752

申请日：2007-12-06

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： A61C17/349 ,  A61C17/3436 ,  Y10T29/49826

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的所需的读数来隐藏存储器件架构的繁忙期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060179262A1

公开(公告)日：2006-08-10

申请号：US11054446

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F13/28

CPC分类号： G06F13/1631

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的读取的读取来隐藏存储器设备架构的繁忙周期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060181942A1

公开(公告)日：2006-08-17

申请号：US11056886

申请日：2005-02-11

申请人： Edgar Cordero ,  James Fields, ,  Kevin Gower ,  Eric Retter

发明人： Edgar Cordero ,  James Fields, ,  Kevin Gower ,  Eric Retter

IPC分类号： G11C29/00

CPC分类号： G06F11/10 ,  G06F11/2007 ,  G11C29/025 ,  G11C2029/0409

摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.

摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。 服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

公开(公告)号：US20060179358A1

公开(公告)日：2006-08-10

申请号：US11054186

申请日：2005-02-09

申请人： Edgar Cordero ,  James Fields ,  Kevin Gower ,  Eric Retter ,  Scott Swaney

发明人： Edgar Cordero ,  James Fields ,  Kevin Gower ,  Eric Retter ,  Scott Swaney

IPC分类号： G06F11/00

CPC分类号： G06F11/1441 ,  G06F11/2028

摘要： A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

摘要翻译： 一种从数据处理系统中的错误中恢复的系统和方法。 数据处理系统包括耦合到一个或多个存储器控制器的一个或多个处理器核心。 一个或多个存储器控制器至少包括耦合到第一存储器的第一存储器接口和耦合到第二存储器的至少第二存储器接口。 响应于确定在第一存储器中检测到错误，禁止经由第一存储器接口访问第一存储器。 此外，第一个存储器接口在本地重新启动，而不重新启动第二个存储器接口。