公开(公告)号：US20060179358A1

公开(公告)日：2006-08-10

申请号：US11054186

申请日：2005-02-09

申请人： Edgar Cordero ,  James Fields ,  Kevin Gower ,  Eric Retter ,  Scott Swaney

发明人： Edgar Cordero ,  James Fields ,  Kevin Gower ,  Eric Retter ,  Scott Swaney

IPC分类号： G06F11/00

CPC分类号： G06F11/1441 ,  G06F11/2028

摘要： A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

摘要翻译： 一种从数据处理系统中的错误中恢复的系统和方法。 数据处理系统包括耦合到一个或多个存储器控制器的一个或多个处理器核心。 一个或多个存储器控制器至少包括耦合到第一存储器的第一存储器接口和耦合到第二存储器的至少第二存储器接口。 响应于确定在第一存储器中检测到错误，禁止经由第一存储器接口访问第一存储器。 此外，第一个存储器接口在本地重新启动，而不重新启动第二个存储器接口。

公开(公告)号：US20060179334A1

公开(公告)日：2006-08-10

申请号：US11054392

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

发明人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在用于操作DIMM和/或DRAM的预定/预设阈值功率/温度值以上的热点。 存储器控制器逻辑基于从特定DIMM / DRAM接收的反馈数据达到预设阈值功率使用值，来限制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20060179184A1

公开(公告)日：2006-08-10

申请号：US11055675

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： G06F3/06 ,  G06F3/02 ,  G06F3/00

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20060176897A1

公开(公告)日：2006-08-10

申请号：US11055404

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US20070073501A1

公开(公告)日：2007-03-29

申请号：US11236449

申请日：2005-09-27

申请人： Andreas Bieswanger ,  Herwig Elfering ,  James Fields ,  Andrew Geissler ,  Alan Hlava ,  Scott Swaney

发明人： Andreas Bieswanger ,  Herwig Elfering ,  James Fields ,  Andrew Geissler ,  Alan Hlava ,  Scott Swaney

IPC分类号： G01N37/00

CPC分类号： G01R31/2894

摘要： A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a single part number. A non-volatile storage is provided on a part, wherein the part includes a plurality of sub-components. Unavailable sub-components in the plurality of sub-components are identified based on a series of testing to form identified unavailable sub-components. Information of the identified unavailable sub-components is stored into the non-volatile storage.

摘要翻译： 计算机实现的方法，数据处理系统和用于使用单个部件号自动识别操作和非操作部件的多个组合的计算机可用程序代码。 在部件上提供非易失性存储器，其中该部件包括多个子部件。 基于一系列测试来识别多个子组件中不可用的子组件，以形成所识别的不可用子组件。 所识别的不可用子组件的信息被存储到非易失性存储器中。

公开(公告)号：US20070088926A1

公开(公告)日：2007-04-19

申请号：US11250022

申请日：2005-10-13

申请人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

IPC分类号： G06F12/14

CPC分类号： G06F12/0831 ,  G06F12/0815 ,  G06F12/0824

摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.

摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控​​制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

公开(公告)号：US20070073919A1

公开(公告)日：2007-03-29

申请号：US11226967

申请日：2005-09-15

申请人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。

公开(公告)号：US20060271741A1

公开(公告)日：2006-11-30

申请号：US11136642

申请日：2005-05-24

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

摘要翻译： 响应于程序代码的执行，用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。 响应于初始化，擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。 响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在 局部一致性域。

公开(公告)号：US20060190636A1

公开(公告)日：2006-08-24

申请号：US11054183

申请日：2005-02-09

申请人： George Daly ,  James Fields

发明人： George Daly ,  James Fields

IPC分类号： G06F13/28

CPC分类号： G06F12/0835 ,  G06F13/28

摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

摘要翻译： 公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。 最初，外围设备发出多高速缓存行DMA请求。 多高速缓存行DMA请求被缓存内存窥探。 然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。 响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。

公开(公告)号：US20060179249A1

公开(公告)日：2006-08-10

申请号：US11055697

申请日：2005-02-10

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Phillip Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。 第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。 主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。