Release layer comprising diamond-like carbon (DLC) or doped DLC with tunable composition for imprint lithography templates and contact masks
    1.
    发明申请
    Release layer comprising diamond-like carbon (DLC) or doped DLC with tunable composition for imprint lithography templates and contact masks 审中-公开
    释放层包括类金刚石碳(DLC)或具有可调组合物的掺杂DLC,用于压印光刻模板和接触掩模

    公开(公告)号:US20060145398A1

    公开(公告)日:2006-07-06

    申请号:US11027473

    申请日:2004-12-30

    CPC classification number: B81C1/0046 B29C33/58 B29C33/60

    Abstract: The present invention pertains to disposing a diamond-like composition on a template, wherein the diamond-like composition acts as a release layer. The diamond-like composition is substantially transparent to actinic radiation, e.g., ultraviolet (UV) light, and will also have a desired surface energy, wherein the desired surface energy minimizes adhesion between the template and an underlying material disposed on a substrate. The diamond-like composition is characterized with a low surface energy that exhibits desirable release characteristics.

    Abstract translation: 本发明涉及在模板上设置类金刚石组合物,其中类金刚石组合物用作剥离层。 类金刚石组合物对于光化辐射(例如紫外线(UV))光是基本上透明的,并且还将具有所需的表面能,其中期望的表面能使最小化模板和布置在基底上的下层材料之间的粘合性。 金刚石组合物的特征在于表现出所需释放特性的低表面能。

    Novel Integration Process to Improve Focus Leveling Within a Lot Process Variation
    2.
    发明申请
    Novel Integration Process to Improve Focus Leveling Within a Lot Process Variation 有权
    新的集成过程,以提高在一个批次过程变化中的焦点调平

    公开(公告)号:US20120112302A1

    公开(公告)日:2012-05-10

    申请号:US12941375

    申请日:2010-11-08

    CPC classification number: H01L21/0332 G03F7/091 G03F7/094 G03F9/7026

    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.

    Abstract translation: 描述了改善半导体晶片的聚焦调平响应的方法。 该方法包括在半导体衬底上组合有机和无机或金属近红外(NIR)硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层(ARC)层; 以及在所述ARC层上形成光致抗蚀剂层。 还描述了半导体结构,其包括基板,位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。 吸收层包括无机或金属NIR吸收硬掩模层。

    Integration of pore sealing liner into dual-damascene methods and devices
    3.
    发明申请
    Integration of pore sealing liner into dual-damascene methods and devices 有权
    将密封衬垫整合到双镶嵌方法和装置中

    公开(公告)号:US20070117371A1

    公开(公告)日:2007-05-24

    申请号:US11286877

    申请日:2005-11-23

    CPC classification number: H01L21/76831 H01L21/76844

    Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

    Abstract translation: 装置采用具有孔密封衬垫的镶嵌层,并且包括半导体本体。 包括金属互连的金属互连层形成在半导体本体上。 介电层形成在金属互连层上。 导电沟槽特征和导电通孔特征形成在电介质层中。 孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。 孔密封衬垫基本上不存在于导电通孔特征的底表面上。

    Integration process to improve focus leveling within a lot process variation
    4.
    发明授权
    Integration process to improve focus leveling within a lot process variation 有权
    整合过程可以在很多过程变化中提高焦点调平

    公开(公告)号:US08395228B2

    公开(公告)日:2013-03-12

    申请号:US12941375

    申请日:2010-11-08

    CPC classification number: H01L21/0332 G03F7/091 G03F7/094 G03F9/7026

    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.

    Abstract translation: 描述了改善半导体晶片的聚焦调平响应的方法。 该方法包括在半导体衬底上组合有机和无机或金属近红外(NIR)硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层(ARC)层; 以及在所述ARC层上形成光致抗蚀剂层。 还描述了半导体结构,其包括基板,位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。 吸收层包括无机或金属NIR吸收硬掩模层。

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