公开(公告)号：US08793095B2

公开(公告)日：2014-07-29

申请号：US13044272

申请日：2011-03-09

申请人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

发明人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

IPC分类号： G01R31/00 ,  G06F11/00

CPC分类号： G06F11/267 ,  G01R31/318508

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. The TAM may be implemented in a fabric-to-fabric bridge, enabling testing of IP blocks connected to fabrics on both sides of the bridge.

摘要翻译： 一种测试访问机制（TAM）体系结构，用于促进集成在片上系统（SoC）上的IP块的测试。 TAM架构包括一个测试控制器和一个或多个集成在靠近IP模块的SoC上的测试包装器。 与外部测试仪的输入相对应的测试数据和命令由测试控制器打包，并通过互连结构发送到测试包装机。 测试包装器采用与一个或多个测试端口的接口来向IP块提供测试数据，控制和/或激励信号，以便于IP块的电路级测试。 电路级测试的测试结果通过结构返回测试控制器。 测试包装器可以被配置为通过互连信号，从而通过测试包和通过该结构在测试控制器和IP块之间传输的测试结果来促进IP块的功能测试。 TAM可以在Fabric-to-fabric桥中实现，从而能够测试连接到网桥两侧的Fabric的IP块。

公开(公告)号：US20120232825A1

公开(公告)日：2012-09-13

申请号：US13044272

申请日：2011-03-09

申请人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

发明人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

IPC分类号： G06F19/00

CPC分类号： G06F11/267 ,  G01R31/318508

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. The TAM may be implemented in a fabric-to-fabric bridge, enabling testing of IP blocks connected to fabrics on both sides of the bridge.

摘要翻译： 一种测试访问机制（TAM）体系结构，用于促进集成在片上系统（SoC）上的IP块的测试。 TAM架构包括一个测试控制器和一个或多个集成在靠近IP模块的SoC上的测试包装器。 与外部测试仪的输入相对应的测试数据和命令由测试控制器打包，并通过互连结构发送到测试包装机。 测试包装器采用与一个或多个测试端口的接口来向IP块提供测试数据，控制和/或激励信号，以便于IP块的电路级测试。 电路级测试的测试结果通过结构返回测试控制器。 测试包装器可以被配置为通过互连信号，从而通过测试包和通过该结构在测试控制器和IP块之间传输的测试结果来促进IP块的功能测试。 TAM可以在Fabric-to-fabric桥中实现，从而能够测试连接到网桥两侧的Fabric的IP块。

公开(公告)号：US20050086548A1

公开(公告)日：2005-04-21

申请号：US10295436

申请日：2002-11-15

申请人： Christopher Haid ,  Enrico Carrieri

发明人： Christopher Haid ,  Enrico Carrieri

IPC分类号： G06F1/32 ,  G11C16/30

CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G11C16/30 ,  G11C2207/2227 ,  Y02D10/14 ,  Y02D50/20

摘要： A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a placement of the non-volatile memory array into a stand-by mode in the absence of activity on at least one or more inputs of the non-volatile memory array. Power may be saved automatically without processor intervention by reducing the operating current of the non-volatile memory array. The automatic power savings circuit may provide a chip enable output to an input of stand-by circuitry to control the operation of the standby circuitry without requiring an explicit stand-by command from a processor.

摘要翻译： 诸如闪存阵列的非易失性存储器阵列可以包括用于控制非易失性存储器阵列的待机模式的功率节省电路。 在非易失性存储器阵列的至少一个或多个输入上没有活动的情况下，省电电路可能导致将非易失性存储器阵列置于备用模式。 通过减少非易失性存储器阵列的工作电流，可以自动保存功率，无需处理器干预。 自动省电电路可以向待机电路的输入提供芯片使能输出，以控制备用电路的操作，而不需要来自处理器的明确的待机命令。