公开(公告)号：US08284963B2

公开(公告)日：2012-10-09

申请号：US12196496

申请日：2008-08-22

Applicant: Klaus Krogsgaard ,  Eric Labbe

Inventor： Klaus Krogsgaard ,  Eric Labbe

IPC: H02B1/00 ,  H03F99/00 ,  H03F1/02 ,  H03F3/38 ,  H03F3/68

CPC classification number: H03F3/2173

Abstract: A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two switched signals such that each of the switched signals is associated with one of the processing circuits leaving at least one unassociated processing circuit. A controller circuit is configured to switch one of the switched signals to be associated with one of the unassociated processing circuit(s) upon at least one specified interval such as, for example, at a transition of the switched signal. The circuit may be incorporated into an audio amplifier configured to provide information carried on the switched signals to one or more speakers that provide an audio output. A one-processor circuit approach includes switching frames of a switched signal between positive and negative inputs of a processor circuit to average out errors introduced by the processor circuit.

Abstract translation: 用于减少至少两个切换信号之间的失配效应的电路包括至少三个处理电路，其被配置为接收至少两个切换信号，使得每个切换信号与处理电路中的一个相关联，留下至少一个未关联的处理电路。 控制器电路被配置为在至少一个指定的间隔（例如在切换的信号的转换）之间切换要与非关联处理电路之一相关联的切换信号中的一个。 电路可以并入音频放大器中，音频放大器被配置为将开关信号上承载的信息提供给提供音频输出的一个或多个扬声器。 单处理器电路方法包括在处理器电路的正输入和负输入之间切换切换信号的帧，以平均处理器电路引入的误差。

公开(公告)号：US07701194B2

公开(公告)日：2010-04-20

申请号：US11831237

申请日：2007-07-31

Applicant: Cheng Hsun Lin ,  Qiong M. Li ,  Eric Labbe

Inventor： Cheng Hsun Lin ,  Qiong M. Li ,  Eric Labbe

IPC: G01R23/00

CPC classification number: H03K7/08 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/375

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract translation: 用于检测脉冲宽度调制（PWM）信号的直流（DC）分量的系统包括被配置为向放大器的输入提供至少一个PWM信号的调制器。 DC检测器被配置为根据所选择的PWM信号的开关频率来检测所述至少一个PWM信号中所选择的一个的DC分量。 DC检测器提供至少一个报告信号，其指示所选择的PWM信号相对于预定阈值的DC分量的电平。

公开(公告)号：US20080054950A1

公开(公告)日：2008-03-06

申请号：US11831237

申请日：2007-07-31

Applicant: CHENG HSUN LIN ,  Qiong M. Li ,  Eric Labbe

Inventor： CHENG HSUN LIN ,  Qiong M. Li ,  Eric Labbe

IPC: H03K5/153

CPC classification number: H03K7/08 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/375

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract translation: 用于检测脉冲宽度调制（PWM）信号的直流（DC）分量的系统包括被配置为向放大器的输入提供至少一个PWM信号的调制器。 DC检测器被配置为根据所选择的PWM信号的开关频率来检测所述至少一个PWM信号中所选择的一个的DC分量。 DC检测器提供至少一个报告信号，其指示所选择的PWM信号相对于预定阈值的DC分量的电平。

公开(公告)号：US06346852B1

公开(公告)日：2002-02-12

申请号：US09557364

申请日：2000-04-25

Applicant: Marco Masini ,  Luigi Franchini ,  Eric Labbe

Inventor： Marco Masini ,  Luigi Franchini ,  Eric Labbe

IPC: H03F338

CPC classification number: H03F3/217

Abstract: A class D amplifier includes an input integrating stage and a modulating stage for modulating the integrated input signal output by the integrating stage. The modulating stage uses as a carrier an alternate waveform of a frequency sufficiently higher than the frequency band of the analog input signal. The modulating stage further outputs a digital signal switching between a positive voltage and a negative voltage, and whose average value represents an amplified replica of the input analog signal. The class D amplifier further includes an output power stage producing an output digital signal. A feedback line including a resistor is connected between the output of the output power stage and an input node of an operational amplifier. The class D amplifier also includes a low-pass filter reconstructing an output analog signal, and a delay stage. The delay stage is functionally coupled in the direct path of propagation of the digital signal from the output of the modulating stage to an input of the output power stage. The delay stage delays the digital signal from the output of the modulating stage by a delay. The value of the delay is defined as a function of a desired broadening of the bandwidth and in consideration of the corresponding restriction of the range of variation of the duty cycle of the output digital signal.

Abstract translation: D类放大器包括输入积分级和用于调制由积分级输出的积分输入信号的调制级。 调制级使用充分高于模拟输入信号的频带的频率的交替波形作为载波。 调制级还输出在正电压和负电压之间切换的数字信号，其平均值表示输入的模拟信号的放大副本。 D类放大器还包括产生输出数字信号的输出功率级。 包括电阻器的反馈线连接在输出功率级的输出端和运算放大器的输入节点之间。 D类放大器还包括重构输出模拟信号的低通滤波器和延迟级。 延迟级在数字信号从调制级的输出到输出功率级的输入的直接传播路径中功能耦合。 延迟级延迟了来自调制级的输出的数字信号。 延迟的值被定义为期望的带宽宽度的函数，并且考虑到输出数字信号的占空比的变化范围的相应限制。

公开(公告)号：US07746155B2

公开(公告)日：2010-06-29

申请号：US11094064

申请日：2005-03-30

Applicant: Eric Labbe

Inventor： Eric Labbe

IPC: H03K17/56

CPC classification number: H03K19/0013 ,  H03K17/08122 ,  H03K17/162 ,  H03K2217/0036

Abstract: In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.

Abstract translation: 根据本发明，提供了一种电路和方法，用于为处于断开状态的功率FET提供可切换的强下拉以避免无意或错误导通。 强力下拉提供给功率FET的栅极，以避免在输出摆幅期间无意中导通。 在其他情况下，功率FET的栅极被弱下拉以降低电路中的EMI和电压噪声。 在特定示例性实施例中，本发明提供了一种用于在断开状态下在功率FET的栅极上获得强下拉沿的电路和方法，同时在导通期间提供弱下拉以截止转变。 本发明避免了快速输出转换期间的错误导通，同时保持相对较高的EMI保护。

公开(公告)号：US20090066413A1

公开(公告)日：2009-03-12

申请号：US12196496

申请日：2008-08-22

Applicant: Klaus Krogsgaard ,  Eric Labbe

Inventor： Klaus Krogsgaard ,  Eric Labbe

IPC: H03F3/68

CPC classification number: H03F3/2173

Abstract: A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two switched signals such that each of the switched signals is associated with one of the processing circuits leaving at least one unassociated processing circuit. A controller circuit is configured to switch one of the switched signals to be associated with one of the unassociated processing circuit(s) upon at least one specified interval such as, for example, at a transition of the switched signal. The circuit may be incorporated into an audio amplifier configured to provide information carried on the switched signals to one or more speakers that provide an audio output. A one-processor circuit approach includes switching frames of a switched signal between positive and negative inputs of a processor circuit to average out errors introduced by the processor circuit.

Abstract translation: 用于减少至少两个切换信号之间的失配效应的电路包括至少三个处理电路，其被配置为接收至少两个切换信号，使得每个切换信号与处理电路中的一个相关联，留下至少一个未关联的处理电路。 控制器电路被配置为在至少一个指定的间隔（例如在切换的信号的转换）之间切换要与非关联处理电路之一相关联的切换信号中的一个。 电路可以并入音频放大器中，音频放大器被配置为将开关信号上承载的信息提供给提供音频输出的一个或多个扬声器。 单处理器电路方法包括在处理器电路的正输入和负输入之间切换切换信号的帧，以平均处理器电路引入的误差。

公开(公告)号：US20060220699A1

公开(公告)日：2006-10-05

申请号：US11094064

申请日：2005-03-30

Applicant: Eric Labbe

Inventor： Eric Labbe

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K17/08122 ,  H03K17/162 ,  H03K2217/0036

Abstract: In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.

Abstract translation: 根据本发明，提供了一种电路和方法，用于为处于断开状态的功率FET提供可切换的强下拉以避免无意或错误导通。 强力下拉提供给功率FET的栅极，以避免在输出摆幅期间无意中导通。 在其他情况下，功率FET的栅极被弱下拉以降低电路中的EMI和电压噪声。 在特定示例性实施例中，本发明提供了一种用于在断开状态下在功率FET的栅极上获得强下拉沿的电路和方法，同时在导通期间提供弱下拉以截止转变。 本发明避免了快速输出转换期间的错误导通，同时保持相对较高的EMI保护。

公开(公告)号：US20060208798A1

公开(公告)日：2006-09-21

申请号：US11079982

申请日：2005-03-15

Applicant: Eric Labbe

Inventor： Eric Labbe

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F2200/462

Abstract: A method of operating a class D amplifier output stage that compensates for nonlinearity introduced by a residual load current during the dead time in the switching of the output stage. The amplifier output stage includes an input, a gate driver circuit, two output transistors, an output, and a current sensing circuit. The transistors are serially connected between the terminals of a power supply. A residual load current flows through the transistors when they are switched off. The gate driver circuit increases or decreases the duty cycles of signals driving the transistors based on the direction of the residual load current flowing through the transistors, thereby causing the duty cycle of the amplifier output to remain substantially constant and equal to the duty cycle of the amplifier input.

Abstract translation: 一种操作D类放大器输出级的方法，其在输出级的切换期间，在死区时间内补偿由剩余负载电流引入的非线性。 放大器输出级包括输入，栅极驱动电路，两个输出晶体管，输出和电流检测电路。 晶体管串联连接在电源的端子之间。 当晶体管关断时，剩余负载电流流过晶体管。 栅极驱动器电路基于流过晶体管的剩余负载电流的方向来增加或减少驱动晶体管的信号的占空比，从而使放大器输出的占空比基本上保持恒定并等于 放大器输入