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公开(公告)号：US20100312991A1
公开(公告)日：2010-12-09
申请号：US12748102
申请日：2010-03-26
CPC分类号： G06F9/30178 , G06F9/3001 , G06F9/30043 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30189 , G06F9/322
摘要： A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions, including instructions with encoded arguments determined by statistical analysis and instructions that have the effect of combinations of instructions.
摘要翻译： 重新编码的指令集架构（ISA）提供较小的位宽指令或较小和较大位宽指令的组合，以提高指令执行效率并减少代码占用。 ISA可以从具有较大位宽指令的传统ISA重新编码，并且重新编码的ISA可以保持与从其导出的ISA的汇编级兼容性。 此外，重新编码的ISA可以具有新的和不同类型的附加指令，包括具有通过统计分析确定的编码参数的指令和具有指令组合的指令的指令。
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公开(公告)号：US07360203B2
公开(公告)日：2008-04-15
申请号：US10774193
申请日：2004-02-06
IPC分类号： G06F9/45
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译： 多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。 线程ID附加到获取位集合的指令和操作数。 多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。 线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。
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公开(公告)号：US07296134B2
公开(公告)日：2007-11-13
申请号：US10777570
申请日：2004-02-11
CPC分类号： G06F12/04
摘要： A microprocessor system includes an address generator, an address selector, and memory system having multiple memory towers, which can be independently addressed. The address generator simultaneously generates a first memory address and a second memory address that is 1 row greater than the first memory address. The address selector determines whether the row portion of the first memory address or the second memory address is used for each memory tower. Because each tower can be addressed independently, a single memory access can be used to access data spanning multiple rows of the memory system.
摘要翻译： 微处理器系统包括地址发生器，地址选择器和具有多个存储器塔的存储器系统，其可以被独立地寻址。 地址产生器同时产生比第一存储器地址大1行的第一存储器地址和第二存储器地址。 地址选择器确定第一存储器地址的行部分或第二存储器地址是否用于每个存储器塔。 因为每个塔都可以独立寻址，所以可以使用单个存储器访问来访问跨越多行存储器系统的数据。
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公开(公告)号：US06859873B2
公开(公告)日：2005-02-22
申请号：US09878145
申请日：2001-06-08
CPC分类号： G06F9/3824 , G06F9/3867
摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.
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公开(公告)号：US20120030392A1
公开(公告)日：2012-02-02
申请号：US12847772
申请日：2010-07-30
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , G06F9/30101 , G06F9/30116 , G06F9/327 , G06F9/4812
摘要： A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented
摘要翻译： 提供一种处理系统，包括中断引脚，多个寄存器，堆栈指针和自动中断系统。 多个寄存器存储多个处理器状态值。 当系统检测到中断引脚上的中断时，系统准备进入异常模式，其中自动中断系统导致中断向量被取出，要更新的堆栈指针，以及要从中更新的并行读取的处理器状态值 在执行中断服务程序之前，基于更新的堆栈指针，将其存储在存储单元中。 还介绍了一种自动硬件中断处理的方法
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6.发明授权Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation 有权嵌入式多线程处理器中的中断和陷阱处理，以避免优先级倒置并保持实时操作公开(公告)号：US07774585B2
公开(公告)日：2010-08-10
申请号：US10712473
申请日：2003-11-12
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26
摘要： A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
摘要翻译： 一个实时的多线程嵌入式系统包括处理陷阱和中断的规则，以避免诸如优先级倒置和重入的问题。 通过为所有活动线程定义全局中断优先级值，并且仅接受优先级高于中断优先级值的中断，可以避免优先级反转。 在任何中断服务之前切换到同一个线程，并且在中断服务期间禁用中断和线程切换可以简化中断处理逻辑。 通过仅在其始发线程中存储陷阱和维护陷阱的陷阱后台数据，可以保留陷阱跟踪性。 通过在陷阱维护期间禁用中断和线程切换，可以防止意外的陷阱重入和服务中断。
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公开(公告)号：US07263599B2
公开(公告)日：2007-08-28
申请号：US10774226
申请日：2004-02-06
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译： 多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。 线程ID附加到获取位集合的指令和操作数。 多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。 线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。
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8.发明授权Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events 有权多线程嵌入式处理器使用确定性指令存储器来保证在阻塞事件期间预先选择的线程的执行公开(公告)号：US07062606B2
公开(公告)日：2006-06-13
申请号：US10431996
申请日：2003-05-07
申请人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
发明人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3851 , G06F12/126 , G06F2212/2515 , Y02D10/13
摘要： A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.
摘要翻译： 一种多线程嵌入式处理器，其包括持续存储与一个或多个预选高使用线程相关联的所有指令的片上确定性（例如，划伤或锁定的高速缓存）存储器。 处理器通过从便宜的外部存储器读取指令（例如，通过片上标准高速缓冲存储器）或使用其他潜在的慢速非确定性操作（例如来自该外部存储器的直接执行）来执行通用（未选择）线程 这可能导致处理器在等待指令到达时停止。 当在一般线程的执行期间出现高速缓存未命中或其他阻塞事件时，处理器切换到预先选择的线程，该线程的执行以零或最小延迟由确定性存储器保证，从而利用其他浪费的处理器周期，直到阻塞事件 做完了。
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9.发明申请VARIABLE REGISTER AND IMMEDIATE FIELD ENCODING IN AN INSTRUCTION SET ARCHITECTURE 有权指令集结构中的变量寄存器和即时编码公开(公告)号：US20100287359A1
公开(公告)日：2010-11-11
申请号：US12464027
申请日：2009-05-11
申请人： Erik K. Norden
发明人： Erik K. Norden
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30156 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30178 , G06F9/30189
摘要： A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.
摘要翻译： 一种方法和装置提供用于压缩指令代码大小的装置。 指令集架构（ISA）对紧凑的，通常的或扩展的位长度进行编码。 通常使用的指令被编码，具有紧凑和通常的位长度，其中基于功率，性能或代码尺寸要求选择的紧凑或通常的位长度指令。 ISA的指令可用于微处理器的特权和非特权操作模式。 指令编码可以在软件应用中互换使用。 来自ISA的指令可以在为ISA启用的任何可编程设备上执行，包括单个指令集架构处理器或多指令集架构处理器。
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公开(公告)号：US20090282220A1
公开(公告)日：2009-11-12
申请号：US12463330
申请日：2009-05-08
申请人： Erik K. Norden
发明人： Erik K. Norden
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3001 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30178 , G06F9/30189 , G06F9/322 , G06F9/3842
摘要： A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions and can be used to unify one or more ISA extensions such as application specific ASEs. The re-encoded ISA maintains assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions.
摘要翻译： 重新编码的指令集架构（ISA）提供较小的位宽指令或较小和较大位宽指令的组合，以提高指令执行效率并减少代码占用。 ISA可以从具有较大位宽指令的传统ISA重新编码，并可用于统一一个或多个ISA扩展，例如特定应用程序的ASE。 重新编码的ISA保持与其派生的ISA的汇编级兼容性。 此外，重新编码的ISA可以具有新的和不同类型的附加指令。
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