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1.发明授权Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock 有权用于通过延迟和扭曲参考时钟来从存储器件补偿数据输出信号中的占空比失真的方法和装置公开(公告)号：US06895522B2
公开(公告)日：2005-05-17
申请号：US09809608
申请日：2001-03-15
申请人： James B. Johnson , Feng D. Lin
发明人： James B. Johnson , Feng D. Lin
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4076 , G11C11/4093 , H04L5/00 , H04L7/00
CPC分类号： G11C7/22 , G06F1/12 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
摘要翻译： 提供了用于补偿由同步动态随机存取存储器件（SDRAM）产生的输出数据信号中的占空比失真的技术。 SDRAM的输出锁存器由延迟锁定环（DLL）产生的输出时钟信号驱动。 输出时钟信号相对于由DLL接收的参考时钟信号相移，使得从输出锁存器移除的数据与参考时钟信号同步。 此外，输出时钟信号的占空比以与由输出锁存器引入的占空比失真相反的关系被调整。 结果，输出数据信号具有减小的占空比失真。
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2.发明授权公开(公告)号：US07206956B2
公开(公告)日：2007-04-17
申请号：US11351277
申请日：2006-02-08
申请人： James B. Johnson , Feng D. Lin
发明人： James B. Johnson , Feng D. Lin
CPC分类号： G11C7/22 , G06F1/12 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
摘要翻译： 提供了用于补偿由同步动态随机存取存储器件（SDRAM）产生的输出数据信号中的占空比失真的技术。 SDRAM的输出锁存器由延迟锁定环（DLL）产生的输出时钟信号驱动。 输出时钟信号相对于由DLL接收的参考时钟信号相移，使得从输出锁存器移除的数据与参考时钟信号同步。 此外，输出时钟信号的占空比以与由输出锁存器引入的占空比失真相反的关系被调整。 结果，输出数据信号具有减小的占空比失真。
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公开(公告)号：US07028208B2
公开(公告)日：2006-04-11
申请号：US11018810
申请日：2004-12-21
申请人： James B. Johnson , Feng D. Lin
发明人： James B. Johnson , Feng D. Lin
CPC分类号： G11C7/22 , G06F1/12 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
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