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    THROUGH-SUBSTRATE VIA AND REDISTRIBUTION LAYER WITH METAL PASTE
    2.
    发明申请
    THROUGH-SUBSTRATE VIA AND REDISTRIBUTION LAYER WITH METAL PASTE 有权
    通过基底和重新分配层与金属膏

    公开(公告)号：US20110210452A1

    公开(公告)日：2011-09-01

    申请号：US13126286

    申请日：2009-10-21

    申请人： Freddy Roozeboom ,  Eric Cornelis Egbertus Van Grunsven ,  Franciscus Hubertus Marie Sanders ,  Maria Mathea Antonetta Burghoorn

    发明人： Freddy Roozeboom ,  Eric Cornelis Egbertus Van Grunsven ,  Franciscus Hubertus Marie Sanders ,  Maria Mathea Antonetta Burghoorn

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/49827 ,  H01L21/4846 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2924/1301 ,  H01L2924/1461 ,  H01L2924/00

    摘要： The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate (5) comprising at least part of an electronic circuit (7) provided at a first side thereof. The substrate (5) comprises a passivation layer (19) at the first side and a substrate via that extends from the first side to a via depth beyond a depth of the electronic circuit (7) such that it is reconfigurable into a through-substrate via (10) by backside thinning of the substrate (5). The semiconductor device further comprises: a patterned masking layer (15) on the first side of the substrate (5). The patterned masking layer (15) comprises at least a trench (16) extending fully through the patterned masking layer (15). The trench has been filled with a redistribution conductor (20). The substrate via and the redistribution conductor (20) comprise metal paste (MP) and together form one piece. The effect of the features of the semi-conductor device of the invention is that there is no physical interface between those the through-substrate via (10) and the redistribution conductor (20). As a consequence of the invention the parasitic resistance of this electrical connection is reduced, which results in a better electrical performance of the semiconductor device. The invention further relates to a method of manufacturing such semiconductor device. And the invention relates to a semiconductor assembly comprising a stacked configuration of a plurality of such semiconductor devices.

    摘要翻译： 本发明涉及一种用于半导体器件和另一半导体器件的叠层结构的半导体器件。 半导体器件包括：衬底（5），其包括设置在其第一侧的电子电路（7）的至少一部分。 衬底（5）包括在第一侧处的钝化层（19）和衬底通孔，其从第一侧延伸到超过电子电路（7）的深度的通孔深度，使得其可重新配置成贯穿衬底 通过（10）通过衬底（5）的背面变薄。 半导体器件还包括：在衬底（5）的第一侧上的图案化掩模层（15）。 图案化掩模层（15）包括至少一个完全延伸穿过图案化掩模层（15）的沟槽（16）。 沟槽已经填充有再分布导体（20）。 衬底通孔和再分布导体（20）包括金属膏（MP）并且一起形成一片。 本发明的半导体器件的特征的效果在于通孔（10）和再分布导体（20）之间没有物理界面。 作为本发明的结果，该电连接的寄生电阻降低，这导致半导体器件的更好的电性能。 本发明还涉及制造这种半导体器件的方法。 本发明涉及包括多个这样的半导体器件的叠层结构的半导体组件。