Linearity enhancement of capacitive transducers by auto-calibration using on-chip neutralization capacitors and linear actuation
    1.
    发明授权
    Linearity enhancement of capacitive transducers by auto-calibration using on-chip neutralization capacitors and linear actuation 有权
    通过使用片上中和电容器和线性驱动的自动校准,电容式换能器的线性增强

    公开(公告)号:US09032777B2

    公开(公告)日:2015-05-19

    申请号:US13235334

    申请日:2011-09-16

    摘要: A system and method are disclosed for automatically calibrating capacitive transducers to neutralize feed-through capacitance using linear actuation. The method includes starting with an initial neutralization capacitance, applying no electrostatic force and two known electrostatic forces to a proof mass of the transducer, recording the transducer output changes due to the applied forces; and determining how to revise neutralization capacitance based on the changes. The method can use a binary search to find a final neutralization capacitance providing the best linearity. The method can include comparing the final linearity to a threshold linearity. The electrostatic forces can be applied using a charge control method where the electrostatic force is a linear function of the actuation duration. The linear actuation can be used for continuous self-test of capacitive sensors.

    摘要翻译: 公开了一种系统和方法,用于自动校准电容式换能器,以使用线性驱动中和馈通电容。 该方法包括从初始中和电容开始,不将静电力和两个已知的静电力施加到换能器的检测质量块,记录由于施加的力引起的换能器输出变化; 并根据变化确定如何修正中和电容。 该方法可以使用二进制搜索来找到提供最佳线性度的最终中和电容。 该方法可以包括将最终线性度与阈值线性度进行比较。 可以使用电荷控制方法施加静电力,其中静电力是致动持续时间的线性函数。 线性驱动可用于电容式传感器的连续自检。

    SURFACE CHARGE REDUCTION TECHNIQUE FOR CAPACITIVE SENSORS

    公开(公告)号:US20130049774A1

    公开(公告)日:2013-02-28

    申请号:US13220457

    申请日:2011-08-29

    IPC分类号: G01R27/26

    CPC分类号: G01D5/24 G01P15/125

    摘要: A differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system. The first core a first input coupled to a first capacitor, a second input coupled to a second capacitor, and a first output. The second core includes a third input coupled to a third capacitor, a fourth input coupled to a fourth capacitor, and a second output. The chopping system has first and fourth inputs coupled to positive signals, and second and third inputs coupled to negative signals. As the chopping system switches between high and low states, it couples the core inputs to different polarity signals reducing charge buildup. The different polarity signals can have substantially same magnitudes. Chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs. The system can include an integrator circuit and differential summing circuits.

    Flicker noise reduction in continuous time (CT) sigma delta modulators (SDMS)
    3.
    发明授权
    Flicker noise reduction in continuous time (CT) sigma delta modulators (SDMS) 有权
    连续时间(CT)Σ-Δ调制器(SDMS)中的闪烁噪声降低

    公开(公告)号:US07791518B2

    公开(公告)日:2010-09-07

    申请号:US12171777

    申请日:2008-07-11

    IPC分类号: H03M1/66

    CPC分类号: H03M3/344 H03M3/408 H03M3/454

    摘要: Embodiments of a system for processing a signal may include a receiver configured to receive an input analog signal and an up converter coupled with the receiver and configured to up convert the analog signal to an up converted analog signal. Embodiments may further include an amplifier coupled with the up converter and configured to amplify the up converted analog signal to generate an amplified signal and also a bandpass filter coupled with the amplifier and configured to filter the amplified signal to generate a filtered analog signal. According to embodiments, the filtered analog signal may be fed to a quanitizer of the ADC. Intermediate signals made thus avoid the flicker noise region typically associated with an integrator of the ADC and may minimize the quantization noise associated with converting higher frequency analog signals.

    摘要翻译: 用于处理信号的系统的实施例可以包括被配置为接收输入模拟信号的接收器和与接收器耦合的上变频器,并且被配置为将模拟信号上变频为上变频的模拟信号。 实施例还可以包括与上变频器耦合的放大器,其被配置为放大上变频的模拟信号以产生放大信号,并且还配置有与放大器耦合的带通滤波器,并配置成对放大的信号进行滤波以产生经滤波的模拟信号。 根据实施例,经滤波的模拟信号可以馈送到ADC的量化器。 所产生的中间信号避免了通常与ADC的积分器相关联的闪烁噪声区域,并且可以最小化与转换较高频率模拟信号相关联的量化噪声。

    Chopping technique for continuous time sigma-delta ADCs without Q-noise folding
    4.
    发明申请
    Chopping technique for continuous time sigma-delta ADCs without Q-noise folding 有权
    连续时间Σ-ΔADC的斩波技术,无Q噪声折叠

    公开(公告)号:US20100164616A1

    公开(公告)日:2010-07-01

    申请号:US12317953

    申请日:2008-12-31

    IPC分类号: H03F1/02

    摘要: A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an output of the transconductor input stage, the chopping switch having a switch output; and a cascode transistor, wherein the switch output is coupled to an output of the chopping transconductor through the cascode transistor. The chopping transconductor may be used in an analog-to-digital converter to isolate chopping switches from junctions with quantization noise.

    摘要翻译: 斩波跨导体包括与斩波晶体管的输入信号耦合的跨导体输入级; 斩波开关与跨导体输入级的输出端耦合,斩波开关具有开关输出; 和共源共栅晶体管,其中开关输出通过共源共栅晶体管耦合到斩波跨导体的输出端。 斩波跨导器可以用于模数转换器,以将斩波开关与量化噪声的接点隔离开来。

    Systems and methods for low power clock generation
    5.
    发明申请
    Systems and methods for low power clock generation 有权
    低功耗时钟发生的系统和方法

    公开(公告)号:US20070273485A1

    公开(公告)日:2007-11-29

    申请号:US11430391

    申请日:2006-05-08

    IPC分类号: H04Q5/22

    CPC分类号: G06F1/3203 Y02D10/126

    摘要: Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver. The radio frequency energy receiver is operable to receive a radio frequency energy and to convert the radio frequency energy to a DC current. In addition, the device further includes a first clock generator that generates a first clock at a first frequency and second clock generator that generates another clock based on the first clock. The first clock generator includes a duty cycle correction circuit. The second clock has a positive going clock edge for each edge of the first clock.

    摘要翻译: 本文描述了用于低功率识别的各种系统和方法。 例如,包括射频能量接收器的射频装置。 射频能量接收器可操作以接收射频能量并将射频能量转换成直流电流。 另外,该装置还包括:第一时钟发生器,其以第一频率产生第一时钟;第二时钟发生器,其基于第一时钟产生另一个时钟。 第一时钟发生器包括占空比校正电路。 第二个时钟对于第一个时钟的每个边沿都有一个正向时钟沿。

    Voltage regulation circuit for RFID systems
    6.
    发明申请
    Voltage regulation circuit for RFID systems 有权
    RFID系统的电压调节电路

    公开(公告)号:US20070046474A1

    公开(公告)日:2007-03-01

    申请号:US11213063

    申请日:2005-08-26

    IPC分类号: G08B13/14

    CPC分类号: G06K19/0723 G06K19/0701

    摘要: A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage limiter circuit. The voltage limiter generates a limited voltage. A voltage regulator is coupled to the limited voltage for generating a regulated output voltage. The voltage regulator has a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

    摘要翻译: 一种用于RFID电路的电压调节电路,具有包括用于感测通过限压器电路的电流的电流检测元件的限压器电路。 电压限制器产生有限的电压。 电压调节器耦合到限制电压以产生稳定的输出电压。 电压调节器具有响应于感测元件的输出的动态偏置电流,用于在电压限制器电路中的电流增加时增加电压调节器的带宽。

    Readout circuit for self-balancing capacitor bridge
    7.
    发明授权
    Readout circuit for self-balancing capacitor bridge 有权
    自平衡电容桥读出电路

    公开(公告)号:US09151774B2

    公开(公告)日:2015-10-06

    申请号:US13551753

    申请日:2012-07-18

    摘要: A capacitive transducer and a readout circuit for processing a signal from a capacitive transducer. The readout circuit includes a high gain circuit element, two summing amplifiers and two feedback path. The high gain circuit element generates an amplified transducer signal, and the summing amplifiers sum the amplified transducer signal with a positive reference voltage and the negative reference voltage, respectively, to generate a first summation signal and a second summation signal. The feedback paths feed back the summation signals to the transducer. Output circuitry generates an output signal based on the summation signals. The high gain circuit element can be a switched capacitor integrator. The output circuitry can generates the output signal based on the first and second summation signals.

    摘要翻译: 一种用于处理来自电容式换能器的信号的电容式换能器和读出电路。 读出电路包括高增益电路元件,两个求和放大器和两个反馈路径。 高增益电路元件产生放大的换能器信号,并且求和放大器将放大的换能器信号分别与正参考电压和负参考电压相加,以产生第一求和信号和第二求和信号。 反馈路径将求和信号反馈到换能器。 输出电路根据求和信号产生输出信号。 高增益电路元件可以是开关电容积分器。 输出电路可以基于第一和第二求和信号产生输出信号。

    SCHEME TO ACHIEVE ROBUSTNESS TO ELECTROMAGNETIC INTERFERENCE IN INERTIAL SENSORS
    8.
    发明申请
    SCHEME TO ACHIEVE ROBUSTNESS TO ELECTROMAGNETIC INTERFERENCE IN INERTIAL SENSORS 有权
    在惯性传感器中实现电磁干扰的方案

    公开(公告)号:US20130063165A1

    公开(公告)日:2013-03-14

    申请号:US13231944

    申请日:2011-09-13

    IPC分类号: G01R27/26 H01G7/00

    摘要: A capacitive sensor system and method resistant to electromagnetic interference is disclosed. The system includes a capacitive core, differential amplifier with inverting and non-inverting inputs, capacitive paths, and chopping system. Core can include inputs and outputs coupled to variable capacitors, and common nodes coupling variable capacitors. Capacitive paths couple core outputs to amplifier inputs. When chopping system is high, one polarity voltage is applied to core inputs, a first core output is coupled to the inverting input and a second core output is coupled to the non-inverting input. When the chopping system is low, opposite polarity voltage is applied to core inputs, and core output to amplifier input couplings are flipped. Capacitive paths can include bond wires. Chopping system can be varied between high and low at frequencies that smear noise away from a frequency band of interest, or that smear noise substantially evenly across a wide frequency range.

    摘要翻译: 公开了一种抵抗电磁干扰的电容传感器系统和方法。 该系统包括电容内核,具有反相和非反相输入的差分放大器,电容路径和斩波系统。 核心可以包括耦合到可变电容器的输入和输出以及耦合可变电容器的公共节点。 电容路径将核心输出耦合到放大器输入。 当斩波系统较高时,一个极性电压施加到核心输入,第一个核心输出耦合到反相输入端,第二个核心输出端耦合到同相输入端。 当斩波系统为低电平时,相反的极性电压被施加到核心输入端,并且芯片输出到放大器输入耦合器被翻转。 电容路径可以包括接合线。 斩波系统可以在高频和低频之间变化,其频率可以从所关心的频带上剔除噪声,或者在宽频率范围内基本均匀地涂抹噪声。

    LINEAR CAPACITANCE-TO-VOLTAGE CONVERTER USING A SINGLE AMPLIFIER FOR ACCELEROMETER FRONT ENDS WITH CANCELLATION OF SPURIOUS FORCES CONTRIBUTED BY SENSOR CIRCUITRY
    9.
    发明申请
    LINEAR CAPACITANCE-TO-VOLTAGE CONVERTER USING A SINGLE AMPLIFIER FOR ACCELEROMETER FRONT ENDS WITH CANCELLATION OF SPURIOUS FORCES CONTRIBUTED BY SENSOR CIRCUITRY 有权
    线性电容电压转换器,使用单个放大器,用于加速度计前端,具有通过传感器电路引起的感觉力的消除

    公开(公告)号:US20130057301A1

    公开(公告)日:2013-03-07

    申请号:US13224144

    申请日:2011-09-01

    IPC分类号: G01R27/26

    摘要: Capacitive transducer systems are disclosed that reduce nonlinearities due to feedthrough capacitances or residual electrostatic forces. The systems can include a core with a first input coupled to a first variable capacitor, a second input coupled to a second variable capacitor, and a core output coupled to a common node; an amplifier with input switchably coupled to common node and an output; a feedback path switchably coupling amplifier output to common node; and a main clock with first and second phases, that controls switches coupling system components. When clock is in first phase, first core input is coupled to reference voltage, second core input is coupled to negative reference voltage, and common node is coupled to amplifier output. When clock is in second phase, core inputs are grounded, and common node is coupled to amplifier input. The system can have single amplifier. Neutralization capacitor can cancel feedthrough and parasitic capacitances.

    摘要翻译: 公开了电容式传感器系统,其减少由馈通电容或残余静电力引起的非线性。 该系统可以包括具有耦合到第一可变电容器的第一输入的第一输入和耦合到第二可变电容器的第二输入以及耦合到公共节点的核心输出的核心; 具有可转换地耦合到公共节点和输出的输入的放大器; 反馈路径将放大器输出切换耦合到公共节点; 以及具有第一和第二相的主时钟,用于控制开关耦合系统组件。 当时钟处于第一阶段时,第一个核心输入耦合到参考电压,第二个核心输入耦合到负参考电压,而公共节点耦合到放大器输出。 当时钟处于第二阶段时,核心输入端接地,公共节点耦合到放大器输入端。 该系统可以有单个放大器。 中和电容可以消除馈通和寄生电容。

    READOUT CIRCUIT FOR SELF-BALANCING CAPACITOR BRIDGE
    10.
    发明申请
    READOUT CIRCUIT FOR SELF-BALANCING CAPACITOR BRIDGE 有权
    自平衡电容桥的读出电路

    公开(公告)号:US20130049525A1

    公开(公告)日:2013-02-28

    申请号:US13220306

    申请日:2011-08-29

    IPC分类号: H02N1/08

    摘要: A capacitive transducer and a readout circuit for processing a signal from a capacitive transducer. The readout circuit includes a high gain circuit element, two summing amplifiers and two feedback path. The high gain circuit element generates an amplified transducer signal, and the summing amplifiers sum the amplified transducer signal with a positive reference voltage and the negative reference voltage, respectively, to generate a first summation signal and a second summation signal. The feedback paths feed back the summation signals to the transducer. Output circuitry generates an output signal based on the summation signals. The high gain circuit element can be a a switched capacitor integrator. The output circuitry can generates the output signal based on the first and second summation signals.

    摘要翻译: 一种用于处理来自电容式换能器的信号的电容式换能器和读出电路。 读出电路包括高增益电路元件,两个求和放大器和两个反馈路径。 高增益电路元件产生放大的换能器信号,并且求和放大器将放大的换能器信号分别与正参考电压和负参考电压相加,以产生第一求和信号和第二求和信号。 反馈路径将求和信号反馈到换能器。 输出电路根据求和信号产生输出信号。 高增益电路元件可以是开关电容器积分器。 输出电路可以基于第一和第二求和信号产生输出信号。