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    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage
    3.
    发明授权
    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
    用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法

    公开(公告)号：US07856607B2

    公开(公告)日：2010-12-21

    申请号：US11934146

    申请日：2007-11-02

    申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F11/24 ,  G01R31/31835

    摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

    摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

    SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE
    4.
    发明申请
    SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE 有权
    用于产生速度快速结构测试以改进过程和环境参数空间覆盖的系统和方法

    公开(公告)号：US20090119629A1

    公开(公告)日：2009-05-07

    申请号：US11934146

    申请日：2007-11-02

    申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F11/24 ,  G01R31/31835

    摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

    摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

    CRITICAL PATH SELECTION FOR AT-SPEED TEST
    5.
    发明申请
    CRITICAL PATH SELECTION FOR AT-SPEED TEST 审中-公开
    用于速度测试的关键路径选择

    公开(公告)号：US20090150844A1

    公开(公告)日：2009-06-11

    申请号：US11954138

    申请日：2007-12-11

    申请人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

    发明人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.

    摘要翻译： 关键路径选择的方法提供了一组最初不包含路径的路径。 定时工具用于识别集成电路设计的潜在关键路径。 如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。 对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。 然后，可以输出该组路径内的潜在关键路径。

    Test path selection and test program generation for performance testing integrated circuit chips
    7.
    发明授权
    Test path selection and test program generation for performance testing integrated circuit chips 有权
    测试路径选择和测试程序生成用于性能测试集成电路芯片

    公开(公告)号：US08543966B2

    公开(公告)日：2013-09-24

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F11/22 ,  G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS
    9.
    发明申请
    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
    性能测试集成电路卡的测试路径选择和测试程序生成

    公开(公告)号：US20130125073A1

    公开(公告)日：2013-05-16

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

    APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING
    10.
    发明申请
    APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING 失效
    在速度测试中选择实现启动扫描能力的装置和方法

    公开(公告)号：US20090106608A1

    公开(公告)日：2009-04-23

    申请号：US11874972

    申请日：2007-10-19

    申请人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

    发明人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/318541

    摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

    摘要翻译： 一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致 被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。