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    CRITICAL PATH SELECTION FOR AT-SPEED TEST
    3.
    发明申请
    CRITICAL PATH SELECTION FOR AT-SPEED TEST 审中-公开
    用于速度测试的关键路径选择

    公开(公告)号：US20090150844A1

    公开(公告)日：2009-06-11

    申请号：US11954138

    申请日：2007-12-11

    申请人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

    发明人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.

    摘要翻译： 关键路径选择的方法提供了一组最初不包含路径的路径。 定时工具用于识别集成电路设计的潜在关键路径。 如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。 对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。 然后，可以输出该组路径内的潜在关键路径。

    Test path selection and test program generation for performance testing integrated circuit chips
    5.
    发明授权
    Test path selection and test program generation for performance testing integrated circuit chips 有权
    测试路径选择和测试程序生成用于性能测试集成电路芯片

    公开(公告)号：US08543966B2

    公开(公告)日：2013-09-24

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F11/22 ,  G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS
    7.
    发明申请
    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
    性能测试集成电路卡的测试路径选择和测试程序生成

    公开(公告)号：US20130125073A1

    公开(公告)日：2013-05-16

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

    METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING
    8.
    发明申请
    METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING 有权
    用于产生用于速度测试的测试模式的方法和装置

    公开(公告)号：US20120191401A1

    公开(公告)日：2012-07-26

    申请号：US13439188

    申请日：2012-04-04

    申请人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F19/00

    CPC分类号： G01R31/318328 ,  G01R31/318342

    摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

    摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

    Method and apparatus for generating test patterns for use in at-speed testing
    9.
    发明授权
    Method and apparatus for generating test patterns for use in at-speed testing 有权
    用于生成用于速度测试的测试模式的方法和装置

    公开(公告)号：US08176462B2

    公开(公告)日：2012-05-08

    申请号：US12464025

    申请日：2009-05-11

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F11/22 ,  G06F17/50

    CPC分类号： G01R31/318328 ,  G01R31/318342

    摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

    摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

    METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING
    10.
    发明申请
    METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING 有权
    用于在速度测试期间覆盖多层过程空间的方法和装置

    公开(公告)号：US20100162064A1

    公开(公告)日：2010-06-24

    申请号：US12340072

    申请日：2008-12-19

    申请人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G01R31/2882

    摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.

    摘要翻译： 在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。 用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试 将会失败，计算基本上确保路径组满足N和M要求并输出用于选择路径集合的度量的度量。