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17 条记录 (耗时 0.017 秒)

    Programmable interconnect point having reduced crowbar current
    1.
    发明授权
    Programmable interconnect point having reduced crowbar current 失效
    可编程互连点具有减少的撬棒电流

    公开(公告)号：US5898320A

    公开(公告)日：1999-04-27

    申请号：US823270

    申请日：1997-03-27

    申请人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

    发明人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

    IPC分类号： H03K19/017

    CPC分类号： H03K19/018585 ,  H03K19/00361

    摘要： Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

    摘要翻译： 通过在电源和地之间插入晶体管开关来解决由于缓冲的可编程互连点处的输入信号转换引起的与过量的短路电流相关的问题。 插入的开关与输入缓冲器串联并由也控制互连的通过/不通过状态的存储器单元控制。 断开插入开关在存储单元输出导致互连的无通状态时，阻断在切换期间流动的电流。

    Fast signal path for programmable logic device
    2.
    发明授权
    Fast signal path for programmable logic device 失效
    可编程逻辑器件的快速信号通路

    公开(公告)号：US5719506A

    公开(公告)日：1998-02-17

    申请号：US533884

    申请日：1995-09-26

    申请人： Sholeh Diba ,  Hy V. Nguyen

    发明人： Sholeh Diba ,  Hy V. Nguyen

    IPC分类号： H03K19/177 ,  H03K7/38 ,  H03K19/0175

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792

    摘要： Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

    摘要翻译： 通过沿设备信号路径提供改进的切换和缓冲来减少可编程逻辑器件中的信号路径的传播延迟。 通过为从给定的设备输入板引出的每个信号路径提供单独的缓冲器来实现这种改进。 以这种方式，缓冲器较小，而不增加净功率消耗。 还提供了改进的输出驱动器，其中设备尺寸被优化以吸收/输出更大量的电流，从而提高设备速度。 包括自举装置的反馈装置提供增加输出缓冲器内提供的电流的路径，从而辅助低到高的信号转换。 还提供了改进的或门，其预充电栅极输出线以确保快速状态转换，同时不需要互补栅极开关逻辑。

    High-speed tristate inverter
    3.
    发明授权
    High-speed tristate inverter 失效
    高速三态变频器

    公开(公告)号：US5399925A

    公开(公告)日：1995-03-21

    申请号：US101131

    申请日：1993-08-02

    申请人： Hy V. Nguyen

    发明人： Hy V. Nguyen

    IPC分类号： H03K19/094 ,  H03K19/00 ,  H03K19/0175

    CPC分类号： H03K19/09429

    摘要： The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.

    摘要翻译： 本发明的三态反相器包括输入线，输出线，用于将高信号传送到输出线的第一晶体管，以及用于将低信号传送到输出线的第二晶体管。 三态反相器还包括用于将输入线与第二晶体管隔离的装置，从而显着地改善输出线上信号的上升时间。

    Single-sided RAM cell and method of accessing same
    6.
    发明授权
    Single-sided RAM cell and method of accessing same 失效
    单面RAM单元及其访问方式

    公开(公告)号：US5877979A

    公开(公告)日：1999-03-02

    申请号：US884369

    申请日：1997-06-26

    申请人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

    发明人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

    IPC分类号： G11C11/412 ,  G11C11/00

    CPC分类号： G11C11/412

    摘要： A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.

    摘要翻译： 提供具有单面存储单元，第一电压供应端子和控制电路的存储器系统。 单面存储单元具有第一节点和第二节点。 通过选择性地将数据信号应用于第一节点或第二节点，将数据值写入存储器单元，并且从第二节点从存储器单元读取数据值。 控制电路被耦合以接收具有第一状态和第二状态之一的数据信号。 当数据信号处于第一状态时，控制电路将存储单元的第一节点耦合到第一电压提供端，从而将第一数据值写入存储单元。 当数据信号处于第二状态时，控制电路将存储单元的第二节点耦合到第一电压供应端，从而将第二数据值写入存储单元。 因为第一电压供应端用于将第一和第二数据值写入存储单元，所以通过适当地选择第一电源电压来消除与写入电压不足有关的问题。

    Configurable bus hold circuit with low leakage current
    9.
    发明授权
    Configurable bus hold circuit with low leakage current 有权
    具有低漏电流的可配置总线保持电路

    公开(公告)号：US06504401B1

    公开(公告)日：2003-01-07

    申请号：US10006548

    申请日：2001-11-30

    申请人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

    发明人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

    IPC分类号： H03K190185

    CPC分类号： H03K19/00315

    摘要： A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

    摘要翻译： 低压输出电路可配置提供总线保持功能和弱上拉功能，同时只有短暂的漏电流通过电路，无论焊盘上的电压电平如何。 因此，输出电路可以用于与高电压器件接口的低电压器件，而不会增加漏电流的损失。 本发明的一个实施例包括耦合到可配置弱上拉电路的电路输出节点，可配置总线保持电路和可配置的防漏电路。 可配置电路由确定哪些电路有效的配置信号控制。 一个实施例被实现为可编程逻辑器件（PLD）的一部分，并且配置信号被编程到配置存储器单元中，作为PLD的配置的一部分。

    Simplified 5V tolerance circuit for 3.3V I/O design
    10.
    发明授权
    Simplified 5V tolerance circuit for 3.3V I/O design 有权
    用于3.3V I / O设计的简化5V容差电路

    公开(公告)号：US06353333B1

    公开(公告)日：2002-03-05

    申请号：US09595780

    申请日：2000-06-16

    申请人： Derek R. Curd ,  Hy V. Nguyen

    发明人： Derek R. Curd ,  Hy V. Nguyen

    IPC分类号： H03K190185

    CPC分类号： H03K19/00315

    摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The output buffer includes a pullup transistor and a pulldown transistor for applying an output signal to an I/O pad. When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Also, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor.

    摘要翻译： 具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。 接口电路包括阻抗控制电路，输出缓冲器，输入缓冲器，隔离电路和上拉保护电路。 输出缓冲器包括用于将输出信号施加到I / O焊盘的上拉晶体管和下拉晶体管。 当高电压（即高于接口电路的内部电压）被施加到I / O焊盘时，上拉保护电路将上拉晶体管的栅极驱动到高I / O焊盘电压，以确保没有电流 流向正电源电压。 此外，隔离电路将高I / O焊盘电压耦合到上拉晶体管的主体（阱），以防止由上拉晶体管形成的寄生二极管的漏电流。