公开(公告)号：US06504401B1

公开(公告)日：2003-01-07

申请号：US10006548

申请日：2001-11-30

申请人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

发明人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

IPC分类号： H03K190185

CPC分类号： H03K19/00315

摘要： A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

摘要翻译： 低压输出电路可配置提供总线保持功能和弱上拉功能，同时只有短暂的漏电流通过电路，无论焊盘上的电压电平如何。 因此，输出电路可以用于与高电压器件接口的低电压器件，而不会增加漏电流的损失。 本发明的一个实施例包括耦合到可配置弱上拉电路的电路输出节点，可配置总线保持电路和可配置的防漏电路。 可配置电路由确定哪些电路有效的配置信号控制。 一个实施例被实现为可编程逻辑器件（PLD）的一部分，并且配置信号被编程到配置存储器单元中，作为PLD的配置的一部分。

公开(公告)号：US06496044B1

公开(公告)日：2002-12-17

申请号：US10016950

申请日：2001-12-13

申请人： Hy V. Nguyen ,  Gubo Huang ,  Andy T. Nguyen

发明人： Hy V. Nguyen ,  Gubo Huang ,  Andy T. Nguyen

IPC分类号： H03K300

CPC分类号： H03K19/01721 ,  H03K19/00315

摘要： Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

摘要翻译： 输出电路，提供与各种输入和输出电压电平的兼容性，而不会牺牲性能。 输出端子上的上拉由内部节点门控，本发明包括用于在该内部节点上放置数据输入信号的各种电路和装置。 一个实施例包括数据输入路径上的电平移位器，同时还提供绕过电平移位器的输出电路的替代路径。 当输入数据值变高时，替代路径会快速地将衰减的高值放在内部节点上。 电平移位器然后变为有效，并将内部节点上的电压提高到输出功率高电平，确保输出上拉完全关闭。

公开(公告)号：US5410189A

公开(公告)日：1995-04-25

申请号：US128387

申请日：1993-09-27

申请人： Hy V. Nguyen

发明人： Hy V. Nguyen

IPC分类号： H03K19/017 ,  H03K5/12

CPC分类号： H03K19/01721

摘要： A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter. The input inverter is then coupled to a driving circuit inverter to provide a CMOS buffer configuration.

摘要翻译： CMOS缓冲器包括输入反相器和耦合到输入反相器的上拉电路。 上拉电路在输入端子的高电平至低信号转换期间，在输入反相器的输出端子上提供额外的临时信号上拉。 上拉电路包括用于产生信号延迟的装置。 在一个实施例中，用于产生信号延迟的装置包括串联的第二和第三反相器，第二反相器接收来自输入反相器的输出信号。 上拉电路还包括用于将高信号传送到输入反相器的输出线的两个晶体管。 一个晶体管由通过用于产生延迟的装置传送的信号控制。 另一个晶体管由输入反相器的输入信号控制。 该上拉电路配置确保从低电平到高电平的信号转换基本上等于输入逆变器的输出线上从高电平到低电平的信号转换。 然后将输入反相器耦合到驱动电路逆变器以提供CMOS缓冲器配置。

公开(公告)号：US08612789B2

公开(公告)日：2013-12-17

申请号：US13005994

申请日：2011-01-13

申请人： Bradley L. Taylor ,  Ting Lu ,  William E. Allaire ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

发明人： Bradley L. Taylor ,  Ting Lu ,  William E. Allaire ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

IPC分类号： G06F1/26

CPC分类号： H03K19/0016 ,  H03K19/177

摘要： An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

摘要翻译： 集成电路可以包括被配置为执行程序代码的处理器系统，其中处理器系统是硬连线的。 IC还可以包括可配置以实现不同物理电路的可编程电路。 可编程电路可以耦合到处理器系统，并且可以被配置为在处理器系统的控制下实现断电过程。

公开(公告)号：US20120221833A1

公开(公告)日：2012-08-30

申请号：US13037234

申请日：2011-02-28

申请人： William E. Allaire ,  Bradley L. Taylor ,  Ting Lu ,  Sandeep Dutta ,  Patrick J. Crotty ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

发明人： William E. Allaire ,  Bradley L. Taylor ,  Ting Lu ,  Sandeep Dutta ,  Patrick J. Crotty ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F13/10 ,  G06F1/26 ,  G06F1/3287 ,  G06F15/7867 ,  G06F15/7871 ,  Y02D10/171

摘要： An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

摘要翻译： 集成电路可以包括被配置为执行程序代码的处理器系统。 处理器系统可以是硬连线的并且包括处理器硬件资源。 IC还可以包括可配置为实现不同物理电路的可编程电路。 可编程电路可以耦合到处理器系统。 可编程电路可以被配置为共享处理器系统的处理器硬件资源的使用。 处理器系统还可以控制诸如上电和/或关断的可编程电路的方面，并且还可以配置可编程电路以在其中实现一个或多个不同的物理电路。

公开(公告)号：US5877979A

公开(公告)日：1999-03-02

申请号：US884369

申请日：1997-06-26

申请人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

发明人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

IPC分类号： G11C11/412 ,  G11C11/00

CPC分类号： G11C11/412

摘要： A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.

摘要翻译： 提供具有单面存储单元，第一电压供应端子和控制电路的存储器系统。 单面存储单元具有第一节点和第二节点。 通过选择性地将数据信号应用于第一节点或第二节点，将数据值写入存储器单元，并且从第二节点从存储器单元读取数据值。 控制电路被耦合以接收具有第一状态和第二状态之一的数据信号。 当数据信号处于第一状态时，控制电路将存储单元的第一节点耦合到第一电压提供端，从而将第一数据值写入存储单元。 当数据信号处于第二状态时，控制电路将存储单元的第二节点耦合到第一电压供应端，从而将第二数据值写入存储单元。 因为第一电压供应端用于将第一和第二数据值写入存储单元，所以通过适当地选择第一电源电压来消除与写入电压不足有关的问题。

公开(公告)号：US5898320A

公开(公告)日：1999-04-27

申请号：US823270

申请日：1997-03-27

申请人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

发明人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

IPC分类号： H03K19/017

CPC分类号： H03K19/018585 ,  H03K19/00361

摘要： Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

摘要翻译： 通过在电源和地之间插入晶体管开关来解决由于缓冲的可编程互连点处的输入信号转换引起的与过量的短路电流相关的问题。 插入的开关与输入缓冲器串联并由也控制互连的通过/不通过状态的存储器单元控制。 断开插入开关在存储单元输出导致互连的无通状态时，阻断在切换期间流动的电流。

公开(公告)号：US5719506A

公开(公告)日：1998-02-17

申请号：US533884

申请日：1995-09-26

申请人： Sholeh Diba ,  Hy V. Nguyen

发明人： Sholeh Diba ,  Hy V. Nguyen

IPC分类号： H03K19/177 ,  H03K7/38 ,  H03K19/0175

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792

摘要： Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

摘要翻译： 通过沿设备信号路径提供改进的切换和缓冲来减少可编程逻辑器件中的信号路径的传播延迟。 通过为从给定的设备输入板引出的每个信号路径提供单独的缓冲器来实现这种改进。 以这种方式，缓冲器较小，而不增加净功率消耗。 还提供了改进的输出驱动器，其中设备尺寸被优化以吸收/输出更大量的电流，从而提高设备速度。 包括自举装置的反馈装置提供增加输出缓冲器内提供的电流的路径，从而辅助低到高的信号转换。 还提供了改进的或门，其预充电栅极输出线以确保快速状态转换，同时不需要互补栅极开关逻辑。

公开(公告)号：US5399925A

公开(公告)日：1995-03-21

申请号：US101131

申请日：1993-08-02

申请人： Hy V. Nguyen

发明人： Hy V. Nguyen

IPC分类号： H03K19/094 ,  H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/09429

摘要： The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.

摘要翻译： 本发明的三态反相器包括输入线，输出线，用于将高信号传送到输出线的第一晶体管，以及用于将低信号传送到输出线的第二晶体管。 三态反相器还包括用于将输入线与第二晶体管隔离的装置，从而显着地改善输出线上信号的上升时间。

公开(公告)号：US06429686B1

公开(公告)日：2002-08-06

申请号：US09595779

申请日：2000-06-16

申请人： Hy V. Nguyen

发明人： Hy V. Nguyen

IPC分类号： H03K19003

CPC分类号： H03K19/00315

摘要： An output driver on an integrated circuit (IC) includes at least one transistor that has a thicker gate oxide than other standard transistors in the IC. In one embodiment, the output driver includes two pull-up transistors. A first pull-up transistor has a thicker gate oxide than standard transistors on the IC to provide a wide range of output voltages on the pad. A second pull-up transistor has a standard, i.e. thin, gate oxide thickness to ensure a fast low-to-high voltage transition on the pad. The other transistors in the output driver have standard gate oxide thicknesses. Illustrative thicknesses include 150 Angstroms for the first pull-up transistor and 50 Angstroms for the second pull-up transistor.

摘要翻译： 集成电路（IC）上的输出驱动器包括至少一个具有比IC中的其它标准晶体管更厚的栅极氧化物的晶体管。 在一个实施例中，输出驱动器包括两个上拉晶体管。 第一上拉晶体管具有比IC上的标准晶体管更厚的栅极氧化物，以在焊盘上提供宽范围的输出电压。 第二上拉晶体管具有标准的，即薄的栅极氧化物厚度，以确保焊盘上的快速的低电平到高电压转变。 输出驱动器中的其他晶体管具有标准栅极氧化物厚度。 示例性的厚度包括用于第一上拉晶体管的150埃和第二上拉晶体管的50埃。