公开(公告)号：US07830178B2

公开(公告)日：2010-11-09

申请号：US11699422

申请日：2007-01-30

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： H03K19/096

CPC分类号： H03K19/0966

摘要： The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

摘要翻译： 动态电路包括：动态节点; 评估电路，用于根据多个输入信号的逻辑评估结果来改变动态节点的充电状态; 控制电路，用于输出逻辑电平根据由评估电路的副本执行的逻辑评估结果而改变的控制信号; 以及用于从控制电路接收控制信号的初始化电路和外部控制信号，以根据控制信号控制动态节点的初始化的开始和停止。

公开(公告)号：US07285985B2

公开(公告)日：2007-10-23

申请号：US11195614

申请日：2005-08-03

申请人： Yukihiro Sasagawa ,  Atsushi Takahata

发明人： Yukihiro Sasagawa ,  Atsushi Takahata

IPC分类号： H03K19/00

CPC分类号： H03K19/0963

摘要： A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plurality of evaluation elements for evaluating data received at a first stage from the signal source to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements evaluates the data input to the evaluation element.

摘要翻译： 逻辑电路包括：事件发生器，用于检测从信号源输出的数据的变化，以产生指示数据变化的事件; 用于以链式方式传播事件的多个传播元件; 以及多个评估元件，用于评估从信号源在第一阶段接收到的数据，以链式方式传播评估结果。 当接收到事件时，多个评估元件中的每一个评估输入到评估元件的数据。

公开(公告)号：US07127594B2

公开(公告)日：2006-10-24

申请号：US10230199

申请日：2002-08-29

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： G06F9/44 ,  G06F9/52

CPC分类号： G06F9/52 ,  G06F9/30076 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885

摘要： A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a program synchronization flag of a program controller. A master processor, responsible for program control of the entire system, notifies an instruction memory section for storing instructions in a program of updated information when the program synchronization flag information is updated.

公开(公告)号：US20050268261A1

公开(公告)日：2005-12-01

申请号：US11136663

申请日：2005-05-25

申请人： Kaori Hatakeyama ,  Yukihiro Sasagawa

发明人： Kaori Hatakeyama ,  Yukihiro Sasagawa

IPC分类号： G06F17/50 ,  G01R27/26 ,  G06F9/45 ,  H01L21/82

CPC分类号： G06F17/5081

摘要： A circuit analyzing device according to the present invention comprises a capacitance value extracting unit for extracting a capacitance value of a functional element from design information including layout information of a semiconductor integrated circuit and a capacitance value outputting unit for displaying the functional element in the semiconductor integrated circuit or a functional-element connecting wiring linked to the functional element on a design drawing including the layout information of the semiconductor integrated circuit in a discriminating manner in accordance with the capacitance value of the functional element, or comprises a per-attribute capacitance value operation unit for executing an operation of the capacitance value per attribute based on a functional-element attribute library in which attribute information of the functional element in the semiconductor integrated circuit is stored and the capacitance value of the functional element and a per-attribute capacitance value outputting unit for outputting the capacitance value per attribute calculated by the per-attribute capacitance value operation unit.

摘要翻译： 根据本发明的电路分析装置包括电容值提取单元，用于从包括半导体集成电路的布局信息的设计信息和用于在半导体集成中显示功能元件的电容值输出单元提取功能元件的电容值 电路或功能元件连接到功能元件的功能元件的设计图，包括根据功能元件的电容值的鉴别方式的半导体集成电路的布局信息，或者包括每属性电容值操作 基于存储半导体集成电路中的功能元件的属性信息的功能元素属性库，执行每个属性的电容值的操作的单元，以及功能元件的电容值和每属性电容 平均值输出单元，用于输出由每个属性电容值操作单元计算的每个属性的电容值。

公开(公告)号：US20080315933A1

公开(公告)日：2008-12-25

申请号：US12133901

申请日：2008-06-05

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

IPC分类号： H03K3/00

CPC分类号： H03K5/00006 ,  H03K5/13

摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

公开(公告)号：US07430678B2

公开(公告)日：2008-09-30

申请号：US11500456

申请日：2006-08-08

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： G06F1/26

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30189 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

摘要： An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

摘要翻译： 目的是在指令解码和前一流水线级的流水线级上执行微处理器的低功率操作，而不需要增加电路尺寸或解码时间。 用于执行指令的每个程序的指令代码包括包括用于指定谓词（301）的标志的第一指令集和包括控制指定信息（302）的一个或多个第二指令集。 根据指令执行控制功能，对每个指令执行每个控制电路的低功率操作。 因此，不需要增加电路尺寸或解码时间，可以控制指令译码和前一流水线级的流水线级，实现微处理器的低功率操作。

公开(公告)号：US07386844B2

公开(公告)日：2008-06-10

申请号：US10760429

申请日：2004-01-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

发明人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

IPC分类号： G06F9/45 ,  G06F1/00 ,  G06F1/26

CPC分类号： G06F9/3001 ,  G06F8/4432 ,  G06F9/30156 ,  G06F9/3836 ,  G06F9/3838 ,  Y02D10/41

摘要： A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

摘要翻译： 编译装置能够产生指令序列，使得处理器以更低的功耗进行操作。 编译装置将源程序转换为用于处理器的机器语言程序，所述处理器包括可并行执行指令的执行单元，并且包括执行单元分别执行执行指令的指令发布单元。 编译器装置包括可解析源程序的解析器单元，可操作以将解析的源程序转换为中间代码的中间代码转换单元，可优化中间代码以减少来自相同指令的指令之间的汉明距离的优化单元 发布单元，并且包括可以将优化的中间代码转换成机器语言指令的代码生成单元。

公开(公告)号：US20070255992A1

公开(公告)日：2007-11-01

申请号：US11785293

申请日：2007-04-17

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： G01R31/31708

摘要： A semiconductor integrated circuit system has a control target circuit executing a program, a system information monitor unit for outputting system information indicating a state of the control target circuit, a circuit characteristic monitor unit for determining a circuit characteristic of the control target circuit and outputting the circuit characteristic as circuit characteristic information, a malfunction determination unit for determining whether or not the control target circuit is normally operating based on the system information, a reference circuit characteristic holding unit for holding the circuit characteristic information as reference circuit characteristic information when the control target circuit is normally operating, a malfunction factor determination unit for determining a malfunction factor based on the circuit characteristic information and on the reference circuit characteristic information when the control target circuit is not normally operating, and a correction target determination unit for determining a correction target in the control target circuit.

摘要翻译： 半导体集成电路系统具有执行程序的控制目标电路，用于输出指示控制对象电路的状态的系统信息的系统信息监视单元，用于确定控制对象电路的电路特性的电路特性监视单元， 电路特性作为电路特性信息，故障判定单元，用于基于系统信息确定控制对象电路是否正常工作;参考电路特性保持单元，用于在电路特性信息保持电路特性信息时作为参考电路特性信息， 电路正常工作;故障因素确定单元，用于当控制目标电路不正常工作时，基于电路特性信息和参考电路特性信息来确定故障因素;以及校正器 用于确定控制目标电路中的校正目标的目标确定单元。

公开(公告)号：US07100063B2

公开(公告)日：2006-08-29

申请号：US10764511

申请日：2004-01-27

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： G06F1/26

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30189 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

摘要： An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

摘要翻译： 目的是在指令解码和前一流水线级的流水线级上执行微处理器的低功率操作，而不需要增加电路大小或解码时间。 用于执行指令的每个程序的指令代码包括包括用于指定谓词（301）的标志的第一指令集和包括控制指定信息（302）的一个或多个第二指令集。 根据指令执行控制功能，对每个指令执行每个控制电路的低功率操作。 因此，不需要增加电路尺寸或解码时间，可以控制指令译码和前一流水线级的流水线级，实现微处理器的低功率操作。

公开(公告)号：US07068565B2

公开(公告)日：2006-06-27

申请号：US10776287

申请日：2004-02-12

申请人： Yukihiro Sasagawa

发明人： Yukihiro Sasagawa

IPC分类号： G11C8/00 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C2207/2227

摘要： Clock control of a sequential circuit is realized with the assumptions that stop of a clock is impossible due to the specifications, and feedback of the output of a memory element does not exist. To this end, the sequential circuit includes a variation detector for detecting a variation occurred in the content of any of master cells which are memory elements included in a master cell group to output a clock control signal, and a clock pulse generator for receiving the clock control signal to generate a clock pulse and supplying the clock pulse to a slave cell which is a memory element included in a clock domain and whose input is varied when the content of any of the master cells which are memory elements included in the master cell group is varied.

摘要翻译： 时序电路的时钟控制是通过假定由于规格而不可能停止时钟，并且存储元件的输出的反馈不存在而实现的。 为此，顺序电路包括变化检测器，用于检测作为主单元组中包括的存储器元件的任何主单元的内容中发生的变化以输出时钟控制信号，以及用于接收时钟的时钟脉冲发生器 控制信号以产生时钟脉冲，并将时钟脉冲提供给作为包括在时钟域中的存储器元件的从单元，并且当作为主单元组中包括的存储元件的任何主单元的内容的输入变化时， 是多样的