公开(公告)号：US06609232B2

公开(公告)日：2003-08-19

申请号：US09791818

申请日：2001-02-26

申请人： Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

发明人： Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

IPC分类号： G06F945

CPC分类号： G06F17/505

摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

摘要翻译： 在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。 对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。 通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。 这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

公开(公告)号：US5936955A

公开(公告)日：1999-08-10

申请号：US964712

申请日：1997-11-05

申请人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

发明人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L29/14 ,  H04J3/24

CPC分类号： H04L49/505 ,  H04L12/56 ,  H04L29/06 ,  H04L47/10 ,  H04L47/32 ,  H04L49/253 ,  H04L69/40 ,  H04L49/30 ,  H04L49/555 ,  H04L69/22 ,  H04L69/329

摘要： A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently received from such one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases such another computer, thereby disconnecting such one computer and such another computer. When reception commands prepared in the buffer area of such another computer are perfectly used, such another computer abandons the packet which does not include the flag to instruct the continuous reception.

摘要翻译： 一种其中多个计算机相互连接的计算机系统的数据通信系统包括：多个计算机，每个计算机具有存储基于该数据通信的命令的区域和用于存储数据的缓冲区; 开关电路，用于相互选择性地连接所述多个计算机; 以及连接在所述开关电路和所述多个计算机中的一个之间的传输允许部件，用于输出信号以允许从所述一台计算机向所述另一计算机的数据传输; 通信部件，用于通过从所述开关电路向所述另一计算机输出从所述传输许可部件发送所述传输许可信号，发送从所述一台计算机接收的数据; 检测部件，用于检测从所述一台计算机到所述另一计算机的关于所述数据通信的异常的发生; 以及通信控制部件，通过根据检测部件的输出输出发送许可信号，放弃随后从这样的计算机接收到的数据。 当异常发生时，开关电路释放这样的另一台计算机，从而断开这样一台计算机和另一台计算机。 当在这样的另一计算机的缓冲区中准备的接收命令被完美地使用时，这样的另一台计算机放弃不包括该标志的分组来指示连续的接收。

公开(公告)号：US5285448A

公开(公告)日：1994-02-08

申请号：US661063

申请日：1991-02-25

申请人： Haruyuki Nakayama ,  Fumio Sukegawa ,  Yoshihiro Takiyasu

发明人： Haruyuki Nakayama ,  Fumio Sukegawa ,  Yoshihiro Takiyasu

IPC分类号： H04J3/08 ,  H04L12/43 ,  H04L12/437 ,  H04Q11/04 ,  H04J3/02 ,  H04J3/12

CPC分类号： H04L12/437 ,  H04J3/085 ,  H04L12/43 ,  H04J2203/0089

摘要： In a system control information transmission system in a ring LAN system, each of a plurality of data transmission devices transmits a transmission frame including a user information transmission area and a system control information transmission area to an adjacent data transmission device at peculiar periods independent of the state of the system, i.e., a failure in the system. The system control information transmission area in the transmission frame is used to transmit system control information only required to be relayed to a downstream data transmission device.

摘要翻译： 在环形LAN系统中的系统控制信息传输系统中，多个数据传输装置中的每一个以独特的时间独立于相邻的数据传输装置发送包括用户信息传输区域和系统控制信息传输区域的传输帧 系统状态，即系统故障。 发送帧中的系统控制信息发送区域用于发送仅需要中继到下游数据发送装置的系统控制信息。

公开(公告)号：US5241543A

公开(公告)日：1993-08-31

申请号：US672640

申请日：1991-03-20

申请人： Eiichi Amada ,  Kunio Hiyama ,  Naoya Kobayashi ,  Yoshihiro Takiyasu ,  Yasuhiko Hatekeyama ,  Haruyuki Nakayama

发明人： Eiichi Amada ,  Kunio Hiyama ,  Naoya Kobayashi ,  Yoshihiro Takiyasu ,  Yasuhiko Hatekeyama ,  Haruyuki Nakayama

IPC分类号： H04J3/06 ,  H04J3/08 ,  H04J3/16 ,  H04L12/42 ,  H04L12/43 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04J3/0623 ,  H04J3/0626 ,  H04J3/0647 ,  H04J3/08 ,  H04J3/1617 ,  H04L12/422 ,  H04L12/43 ,  H04Q11/0478 ,  H04J2203/0042 ,  H04J2203/0082 ,  H04J2203/0089 ,  H04J3/0685 ,  H04L2012/5652 ,  H04L2012/5672

摘要： In a local area network composed of transmission lines for interconnecting a plurality of subordinate networks including synchronous apparatuses and a plurality of nodes which connect the subordinate networks to the transmission lines, information is transferred using a fixed length frame, a clock source which generates an independent clock signal and a circuit which generates a fixed length frame with the oscillation frequency of the clock source as a reference are provided in each node so as to adopt an independent clocking system, and distribution of a common synchronizing clock required for synchronous apparatuses is made by transmission while embedding transition point information of a synchronizing clock in a specific space in the fixed length frame. Further, each node generates a fixed length transmission frame with an independent clock signal, and on the other hand, there are provided in each node, from the requirement that information quantity applied to a network is made constant, a circuit for extracting a received clock, a storage device for storing received information temporarily, and an information outgoing quantity control circuit in which information quantity which is sent out in one frame is increased when the information quantity stored in the storage device becomes more than a predetermined first reference value and information quantity which is sent out in one frame is decreased when the information quantity stored in the storage device becomes less than a predetermined second reference value.

摘要翻译： 在由包括同步装置的多个下属网络和将下属网络连接到传输线路的多个节点互连的传输线路构成的局域网中，使用固定长度的帧传送信息，产生独立的时钟源 时钟信号和以时钟源的振荡频率为基准产生固定长度帧的电路设置在每个节点中，以便采用独立的时钟系统，同步装置所需的公共同步时钟的分配由 同时将同步时钟的转换点信息嵌入固定长度帧中的特定空间中。 此外，每个节点产生具有独立时钟信号的固定长度传输帧，另一方面，从应用于网络的信息量变为恒定的要求，在每个节点中提供用于提取接收时钟的电路 用于临时存储接收到的信息的存储装置，以及信息输出量控制电路，当存储在存储装置中的信息量变得超过预定的第一参考值和信息量时，在一帧中发送的信息量增加 当存储在存储装置中的信息量变得小于预定的第二参考值时，在一帧中发送的信息量减少。

公开(公告)号：US5835492A

公开(公告)日：1998-11-10

申请号：US529762

申请日：1995-09-18

申请人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

发明人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L29/14 ,  H04J3/24

CPC分类号： H04L49/505 ,  H04L12/56 ,  H04L29/06 ,  H04L47/10 ,  H04L47/32 ,  H04L49/253 ,  H04L69/40 ,  H04L49/30 ,  H04L49/555 ,  H04L69/22 ,  H04L69/329

摘要： A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases another computer, thereby disconnecting one computer and another computer. When reception commands prepared in the buffer area of another computer are perfectly used, another computer abandons the packet which does not include the flag to instruct the continuous reception.

摘要翻译： 一种用于计算机相互连接的计算机系统的数据通信系统包括：每个计算机具有存储用于根据其执行数据通信的命令的区域和用于存储数据的缓冲区; 用于相互选择性地连接计算机的开关电路; 以及连接在开关电路和其中一台计算机之间的传输允许部件，用于输出信号以允许从一台计算机到另一台计算机的数据传输; 通信部件，用于通过将所述传输许可部件通过所述开关电路输出到另一计算机的传输许可信号，发送从一台计算机接收的数据; 检测部件，用于检测从一个计算机到另一个计算机的关于数据通信的异常的发生; 以及通信控制部件，通过根据检测部件的输出输出发送允许信号，放弃随后从一台计算机接收到的数据。 当异常发生时，开关电路释放另一台计算机，从而断开一台计算机和另一台计算机的连接。 当在另一计算机的缓冲区中准备的接收命令被完美地使用时，另一台计算机放弃不包括该标志的分组来指示连续接收。

公开(公告)号：US5832303A

公开(公告)日：1998-11-03

申请号：US516392

申请日：1995-08-17

申请人： Shoichi Murase ,  Haruyuki Nakayama ,  Takeshi Aimoto ,  Hiroshi Iwamoto

发明人： Shoichi Murase ,  Haruyuki Nakayama ,  Takeshi Aimoto ,  Hiroshi Iwamoto

IPC分类号： H04L12/56 ,  G06F15/16

CPC分类号： H04L49/1538 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/1576 ,  H04L49/254 ,  H04L49/3081 ,  H04L2012/5679 ,  H04L49/30

摘要： A large-scaled interconnection switch in which a plurality of data processors are interconnected to perform data transfer between one another. The switch includes communication controllers, one provided for each of the plurality of data processors, divided into groups, for controlling communication between the data processors. Each group of communication controllers is connected by a signal line having a multiple bit width. A switch arbiter for arbitrates switch setting requests for interconnection of the data processors from the communication controllers to output a switch setting control signal. The switch also includes bit slice switches having a predetermined bit division count and to which respective/output signal lines are connected which bit-divide input/output signals of the communication controllers. The bit slice switch receives a switch setting control signal from the switch arbiter and transfers data from a transmission data line from a communication controller to a receiving data line to the communication controller on the basis of the switch setting control signal.

摘要翻译： 一种大规模的互连交换机，其中多个数据处理器互连以执行彼此之间的数据传输。 该交换机包括通信控制器，一个为多个数据处理器中的每一个提供分组，用于控制数据处理器之间的通信。 每组通信控制器通过具有多位宽度的信号线连接。 一种用于仲裁开关设置请求的开关仲裁器，用于从通信控制器互连数据处理器以输出开关设置控制信号。 开关还包括具有预定位分割计数的位片开关，并且连接相应/输出信号线的哪个位分割输入/输出通信控制器的信号。 位片开关从开关仲裁器接收开关设定控制信号，并根据开关设定控制信号将数据从通信控制器从通信控制器传输到接收数据线传送到通信控制器。