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公开(公告)号：US07642599B2
公开(公告)日：2010-01-05
申请号：US11331160
申请日：2006-01-13
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L23/62 , H01L27/088
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。
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公开(公告)号：US07170106B2
公开(公告)日：2007-01-30
申请号：US11221702
申请日：2005-09-09
IPC分类号： H01L29/74 , H01L29/423 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US07075168B2
公开(公告)日：2006-07-11
申请号：US11016810
申请日：2004-12-21
IPC分类号： H01L27/102
CPC分类号： H01L29/7397 , H01L29/4232 , H01L29/42372 , H01L29/7395
摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.
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公开(公告)号：US20060081919A1
公开(公告)日：2006-04-20
申请号：US11044065
申请日：2005-01-28
申请人： Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/24
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/66348
摘要： A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer; a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction; a gate electrode formed in said trench via a gate insulating film; a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer; an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and a second-conductivity-type semiconductor layer selectively formed in a region along the longitudinal direction of said trench, near the surface of said first-conductivity-type emitter layer.
摘要翻译： 一种半导体器件，包括：第一导电型基底层; 形成在所述第一导电型基底层的第一主表面上的第二导电型发射极层; 与所述第二导电型发射极层的表面接触地形成的集电极; 形成在所述第一导电型基底层的第二主表面上的第二导电型基底层; 多个沟槽，其延伸穿过所述第二导电型基底层，以达到所述第一导电型基底层的预定深度，并且在一个方向上具有纵向方向; 通过栅极绝缘膜形成在所述沟槽中的栅电极; 在所述第二导电型基底层的表面部分中选择性地形成为与所述沟槽的侧壁接触的第一导电型发射极层; 与所述第二导电型基极层的表面和所述第一导电型发射极层的表面接触形成的发射极; 以及在所述第一导电型发射极层的表面附近，沿着所述沟槽的纵向的区域选择性地形成的第二导电型半导体层。
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公开(公告)号：US20050263852A1
公开(公告)日：2005-12-01
申请号：US10974810
申请日：2004-10-28
IPC分类号： H01L29/78 , H01L27/082 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/739
CPC分类号： H01L29/1095 , H01L29/0834 , H01L29/7397
摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.
摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。
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公开(公告)号：US06917060B2
公开(公告)日：2005-07-12
申请号：US10662295
申请日：2003-09-16
IPC分类号： H01L29/786 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/74
CPC分类号： H01L29/0696 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A vertical semiconductor device including a first conductivity type base layer having resistance higher then of a first conductivity type buffer layer, the first conductivity type buffer layer formed in one surface portion of the first conductivity type base layer, a second conductivity type drain layer selectively formed in a surface portion of the first conductivity type buffer layer, a second conductivity type base layer selectively formed in the other surface portion of the first conductivity type base layer, a first conductivity type source layer selectively formed in a surface portion of the second conductivity type base layer, a gate insulating film formed on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer, a gate electrode formed on the second conductivity type base layer via the gate insulating film, a drain electrode electrically connected to the second conductivity type drain layer, and a source electrode electrically connected to the first conductivity type source layer and the second conductivity type base layer, wherein the drain electrode is not electrically connected to the first conductivity buffer layer.
摘要翻译： 一种垂直半导体器件，包括具有比第一导电型缓冲层高的电阻的第一导电型基极层，形成在第一导电型基极层的一个表面部分中的第一导电型缓冲层，选择性地形成第二导电型漏极层 在第一导电型缓冲层的表面部分中，选择性地形成在第一导电型基底层的另一个表面部分中的第二导电型基极层，选择性地形成在第二导电型基底层的表面部分中的第一导电型源极 形成在第一导电型源极层和第一导电型基极层之间的第二导电型基极层上的栅极绝缘膜，经由栅极绝缘膜形成在第二导电型基极层上的栅极电极，漏极电极 电连接到第二导电类型漏极层，以及sou rce电极与第一导电型源极层和第二导电型基极层电连接，其中漏极电极不与第一导电性缓冲层电连接。
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公开(公告)号：US06891224B2
公开(公告)日：2005-05-10
申请号：US10461345
申请日：2003-06-16
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/78 , H01L21/8228 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/0336 , H01L31/062 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes: a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a well layer of a second conductivity type formed on the barrier layer; a trench formed from the surface of the well layer to such a depth as to reach a region in the vicinity of a junction surface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of the second conductivity type selectively formed in a surface portion of the well layer, a source layer of the first conductivity type selectively formed in the surface portion of the well layer so as to contact a side wall of the gate insulating film in the trench and the contact layer, and a first main electrode formed so as to contact the contact layer and the source layer, wherein assuming that a total sum of impurity densities in the region of the barrier layer between the trenches is Qn, the Qn has a relation of the following equation: Qn≧2×1012 cm−2.
摘要翻译： 半导体器件包括：形成在第一导电类型的基底层，形成在基底层上的第一导电类型的势垒层，形成在阻挡层上的第二导电类型的阱层; 从阱层的表面形成的沟槽到达阻挡层和基底层之间的接合面附近的区域的深度，通过栅极绝缘膜形成在沟槽中的栅电极， 选择性地形成在阱层的表面部分中的第二导电类型的层，选择性地形成在阱层的表面部分中以与沟槽中的栅极绝缘膜的侧壁接触的第一导电类型的源极层 以及形成为与接触层和源极层接触的第一主电极，其中假设沟槽之间的势垒层的区域中的杂质浓度的总和为Qn，则Qn具有关系 具有以下等式：Qn> = 2×10×12
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公开(公告)号：US06809349B2
公开(公告)日：2004-10-26
申请号：US10354048
申请日：2003-01-30
IPC分类号： H01L2974
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
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公开(公告)号：US06703013B1
公开(公告)日：2004-03-09
申请号：US09508539
申请日：2000-04-05
IPC分类号： A61K3774
CPC分类号： A61K9/006 , A61K9/06 , A61K31/795 , Y10S514/944
摘要： The invention relates to a polystyrene sulfonate-containing gel preparation for therapy of hyperpotassemia, wherein the particle size of polystyrene sulfonate is controlled within the range of at least 5-100 &mgr;m, the viscosity of its solution before gelation is adjusted depending on the particle size by adding a thickening agent, and the polystyrene sulfonate particles after gelation is uniformly dispersed therein. More preferably, a water-displacing agent is contained, whereby the amount of water in the preparation is reduced. This gel preparation does not cause a sense of foreign matter or a sense of roughness in the oral cavity upon ingestion and intake, thus making it unnecessary to drink water for ingestion, and further its water content is low, so that control of water intake is made easy, even in the case of a patient with renal insufficiency who is subjecting to restriction in intake of water to significant improve the quality of life of the patient.
摘要翻译： 本发明涉及一种用于治疗高钾血症的聚苯乙烯磺酸盐凝胶制剂，其中聚苯乙烯磺酸盐的粒径控制在至少5-100μm的范围内，凝胶化前溶液的粘度根据粒径 通过添加增稠剂，凝胶化后的聚苯乙烯磺酸酯粒子均匀分散。 更优选含有取代剂，由此减少制剂中的水量。 这种凝胶制剂在摄入和摄入时不会引起口腔感和异味，因此不必饮用水摄取，进一步其含水量低，从而控制摄入水量 即使在患有肾功能不全的患者进行限制摄入水以显着改善患者的生活质量的情况下也是容易的。
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公开(公告)号：US06650001B2
公开(公告)日：2003-11-18
申请号：US10053657
申请日：2002-01-24
IPC分类号： H01L27082
CPC分类号： H01L29/0696 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.
摘要翻译： 横向半导体器件包括：n型缓冲层（15），其选择性地形成在n型基极层（14）的表面; p型漏极层（16），其选择性地形成在n型缓冲层 层（15），形成在n型基底层（14）的表面中以围绕n型缓冲层（15）的p型基底层（17），n +型源 选择性地形成在p型基底层（17）的表面中的层（18），与p型基底层（17）和n +型源极层（18）接触的源极（24） ），与p型漏极层（16）接触的漏电极（22）和在p型基极层（17）的表面上经由栅极绝缘膜（19）形成的栅电极（20） 夹在n +型源极层（18）和n型基极层（14）之间。 p型漏极层（16）具有环状结构或马蹄形结构，或分为多个部分。 这实现了具有低导通电压的高击穿电压。
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