公开(公告)号：US08799798B2

公开(公告)日：2014-08-05

申请号：US12796814

申请日：2010-06-09

申请人： Hidenobu Ito

发明人： Hidenobu Ito

IPC分类号： G06F3/048 ,  G06F3/033 ,  G06F17/30

CPC分类号： G06F17/30867 ,  G06F3/04883 ,  G06F17/3025 ,  G06F17/30259 ,  G06F17/3079 ,  G06F17/30864 ,  G06F17/30997

摘要： Methods and systems for providing navigation assistance on a mobile device are provided. A method may include analyzing handwriting data to recognize one or more objects depicted in the handwriting data. The method may further include determining if one or more applications are associated with the handwriting data based on the one or more objects recognized in the handwriting data. If one application is determined to be associated with the handwriting data, the one application may be launched. If two or more applications are determined to be associated with the handwriting data, information allowing a user to select an application to launch from the two or more applications may be displayed.

摘要翻译： 提供了用于在移动设备上提供导航辅助的方法和系统。 方法可以包括分析手写数据以识别手写数据中描绘的一个或多个对象。 该方法还可以包括基于手写数据中识别的一个或多个对象来确定一个或多个应用是否与手写数据相关联。 如果确定一个应用程序与手写数据相关联，则可以启动一个应用程序。 如果确定两个或多个应用程序与手写数据相关联，则可以显示允许用户选择从两个或更多个应用程序启动的应用程序的信息。

公开(公告)号：US20120269193A1

公开(公告)日：2012-10-25

申请号：US13431010

申请日：2012-03-27

申请人： Zhaogong Guo ,  Kazuaki Nimura ,  Yosuke Nakamura ,  Koichi Yasaki ,  Hidenobu Ito

发明人： Zhaogong Guo ,  Kazuaki Nimura ,  Yosuke Nakamura ,  Koichi Yasaki ,  Hidenobu Ito

IPC分类号： H04L12/56

CPC分类号： H04L49/35

摘要： An apparatus includes first and second processors, a common memory, and a switch. The first processor executes an operating system, connects to a communication network and communicates with the communication network. The second processor operates independently of the operating system, connects to the communication network, and communicates with the communication network. The second processor writes, in the common memory, communication setting information being used by the second processor when the switch switches the connection destination from the second processor to the first processor. The first processor acquires the communication setting information, and sets the acquired communication setting information to the first processor. The switch switches the connection destination of the communication network from the second processor to the first processor after the communication setting information has been set to the first processor.

摘要翻译： 一种装置包括第一和第二处理器，公共存储器和开关。 第一处理器执行操作系统，连接到通信网络并与通信网络进行通信。 第二处理器独立于操作系统操作，连接到通信网络，并与通信网络进行通信。 第二处理器在公共存储器中写入当交换机将连接目的地从第二处理器切换到第一处理器时由第二处理器使用的通信设置信息。 第一处理器获取通信设置信息，并将所获取的通信设置信息设置到第一处理器。 在将通信设置信息设置为第一处理器之后，交换机将通信网络的连接目的地从第二处理器切换到第一处理器。

公开(公告)号：US08203817B2

公开(公告)日：2012-06-19

申请号：US12369907

申请日：2009-02-12

申请人： Morihito Hasegawa ,  Hidenobu Ito ,  Kwok Fai Hui ,  Toshihiko Kasai ,  Katsuyuki Yasukouchi

发明人： Morihito Hasegawa ,  Hidenobu Ito ,  Kwok Fai Hui ,  Toshihiko Kasai ,  Katsuyuki Yasukouchi

IPC分类号： H02H9/08

摘要： A power supply circuit includes an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier powered by the power supply voltage and outputting a signal based on a potential difference between the output voltage and a reference voltage; a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and coupled to a gate of the output transistor; a current detection transistor coupled to the output transistor such that a gate and source are shared; and an overcurrent protection circuit configured to limit the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby control the output current of the output transistor.

公开(公告)号：US07982431B2

公开(公告)日：2011-07-19

申请号：US12031403

申请日：2008-02-14

申请人： Masatoshi Kokubun ,  Takashi Matsumoto ,  Hidenobu Ito

发明人： Masatoshi Kokubun ,  Takashi Matsumoto ,  Hidenobu Ito

IPC分类号： H02J7/00 ,  H02J7/04 ,  H02J7/16

CPC分类号： H02M3/156 ,  G01R19/16542 ,  H02M2001/0009

摘要： A detection circuit that reduces circuit scale. A plurality of current amplifiers respectively generate a plurality of detection signals corresponding to current flowing to a plurality of resistors. An error amplifier coupled to the plurality of current amplifiers compares the plurality of detection signals with a plurality of reference signals, respectively, to generate an error signal based on the comparison.

摘要翻译： 一种降低电路规模的检测电路。 多个电流放大器分别产生对应于流向多个电阻器的电流的多个检测信号。 耦合到多个电流放大器的误差放大器分别将多个检测信号与多个参考信号进行比较，以基于该比较产生误差信号。

公开(公告)号：US20100289471A1

公开(公告)日：2010-11-18

申请号：US12778812

申请日：2010-05-12

申请人： Toshihiko KASAI ,  Hidenobu Ito

发明人： Toshihiko KASAI ,  Hidenobu Ito

IPC分类号： G05F1/10

CPC分类号： H02M3/1588 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： A power control device for performing switching control for an output voltage of a power supply device includes a signal generation circuit for comparing a difference between a value of the output voltage and a value of a first reference voltage with a value of a second reference voltage, and for stopping the switching control when a value of the difference is less than or equal to the value of the second reference voltage, and an adjuster circuit for adjusting the second reference voltage based on a ratio between a value of an input voltage and the value of the output voltage.

摘要翻译： 用于对电源装置的输出电压执行开关控制的功率控制装置包括信号产生电路，用于将输出电压的值和第一参考电压的值与第二参考电压的值进行比较， 并且当所述差的值小于或等于所述第二参考电压的值时停止所述开关控制;以及调节器电路，用于基于输入电压的值和所述值之间的比率来调整所述第二参考电压 的输出电压。

公开(公告)号：US20090115382A1

公开(公告)日：2009-05-07

申请号：US12255356

申请日：2008-10-21

申请人： Morihito HASEGAWA ,  Hidenobu Ito ,  Kwok Fai Hui ,  Yat Fong Yung

发明人： Morihito HASEGAWA ,  Hidenobu Ito ,  Kwok Fai Hui ,  Yat Fong Yung

IPC分类号： G05F1/00

CPC分类号： G05F1/575

摘要： According to one aspect of the embodiment, a linear regulator circuit includes an output transistor outputting an output current based on a input voltage, an error amplifier outputting a control signal based on an electric potential difference between an output voltage based on the output current and a reference voltage, a buffer circuit coupled between the error amplifier and the output transistor, and a drive capability adjustment circuit adjusting a load drive capability of the buffer circuit in synchronization with the output current.

摘要翻译： 根据本实施例的一个方面，线性调节器电路包括输出晶体管，其基于输入电压输出输出电流;误差放大器，基于输出电流的输出电压和基于输出电流的电位差输出控制信号; 参考电压，耦合在误差放大器和输出晶体管之间的缓冲电路，以及与输出电流同步地调节缓冲电路的负载驱动能力的驱动能力调整电路。

公开(公告)号：US07340559B2

公开(公告)日：2008-03-04

申请号：US11256932

申请日：2005-10-25

申请人： Hidenobu Ito ,  Katsutoshi Yano ,  Isamu Yamada

发明人： Hidenobu Ito ,  Katsutoshi Yano ,  Isamu Yamada

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G11C7/00

CPC分类号： G06K7/0008 ,  G06K17/00

摘要： To provide a memory product controller, a memory product control method, and a memory product storing a computer program, capable of realizing a multi-function memory product, without increasing the cost, by grouping a plurality of memory products. In a memory product controller, information identifying a memory product and an operating condition of the memory product are stored in association with information identifying a group, and when reading/writing is performed on one memory product belonging to a predetermined group by a reader/writer for a memory product, reference is made to an operating condition storage unit, and when other memory products having the similar operating condition are present in the same group, instruction information to perform reading or writing on one or a plurality of other memory products belonging to the same group and having the similar operating condition is transmitted to the reader/writer.

摘要翻译： 通过分组多个存储器产品来提供存储产品控制器，存储器产品控制方法和存储计算机程序的存储器产品，其能够实现多功能存储器产品而不增加成本。 在存储器产品控制器中，与识别组的信息相关联地存储识别存储器产品的信息和存储器产品的操作条件，并且当由读写器对属于预定组的一个存储器产品执行读/写时 对于存储器产品，参考操作条件存储单元，并且当具有类似操作条件的其他存储器产品存在于同一组中时，对属于该存储器的一个或多个其他存储器产品执行读取或写入的指令信息 具有类似操作条件的相同组被传送到读/写器。

公开(公告)号：US20060181260A1

公开(公告)日：2006-08-17

申请号：US11402129

申请日：2006-04-12

申请人： Hidenobu Ito

发明人： Hidenobu Ito

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： There are provided a control circuit of a DC-DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption at the stop of power supply, and a control method thereof. While a power supply stop signal is at low level, a control part controls an NMOS transistor according to the output signals of a comparator and a flip-flop circuit. While the power supply stop signal is at high level, the control part masks a reverse current detection signal and the output signal of the flip-flop circuit to control the NMOS transistor according to a detection signal of a comparator. When a choke coil current is reversely flowed and an output voltage is lowered to an output reference voltage corresponding to a reference voltage, the NMOS transistor is brought to the non-conductive state to regenerate the electric power to an input terminal.

公开(公告)号：US20060071651A1

公开(公告)日：2006-04-06

申请号：US11025134

申请日：2004-12-30

申请人： Hidenobu Ito

发明人： Hidenobu Ito

IPC分类号： H02M3/156

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： There are provided a control circuit of a DC-DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption at the stop of power supply, and a control method thereof. While a power supply stop signal is at low level, a control part controls an NMOS transistor according to the output signals of a comparator and a flip-flop circuit. While the power supply stop signal is at high level, the control part masks a reverse current detection signal and the output signal of the flip-flop circuit to control the NMOS transistor according to a detection signal of a comparator. When a choke coil current is reversely flowed and an output voltage is lowered to an output reference voltage corresponding to a reference voltage, the NMOS transistor is brought to the non-conductive state to regenerate the electric power to an input terminal.

摘要翻译： 提供了一种同步整流系统的DC-DC转换器的控制电路及其控制方法，该控制电路能够在停电时实现低功耗的输出电压的快速降低。 当电源停止信号处于低电平时，控制部分根据比较器和触发器电路的输出信号来控制NMOS晶体管。 当电源停止信号处于高电平时，控制部分屏蔽反向电流检测信号和触发器电路的输出信号，以根据比较器的检测信号控制NMOS晶体管。 当扼流线圈电流反向流动并且输出电压降低到与参考电压相对应的输出参考电压时，NMOS晶体管变为非导通状态，以将电力再生为输入端子。

公开(公告)号：US06611132B2

公开(公告)日：2003-08-26

申请号：US10087852

申请日：2002-03-05

申请人： Shinichi Nakagawa ,  Hidenobu Ito

发明人： Shinichi Nakagawa ,  Hidenobu Ito

IPC分类号： G05F140

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0041 ,  Y02B70/16

摘要： A DC-DC converter for decreasing power consumption and quickly increasing an output voltage. The converter includes a voltage generation circuit, a switching control circuit, a current detection circuit, and a step control circuit. An output transistor performs switching to generate the output voltage of the switching control circuit. The current detection circuit is connected to the voltage generation circuit to detect a load current, which is derived from the output voltage, and to generate a detection signal. A stop control circuit maintains the output transistor in an activated state in accordance with the detection signal and stops the operation of the switching control circuit when the load current is less than or equal to the load current.