公开(公告)号：US4489340A

公开(公告)日：1984-12-18

申请号：US228935

申请日：1981-01-28

申请人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Hirokazu Tsukada ,  Kotaro Kato

发明人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Hirokazu Tsukada ,  Kotaro Kato

IPC分类号： H01L27/144 ,  H01L31/111 ,  H04Q3/52 ,  H01L29/74

CPC分类号： H01L31/1113 ,  H01L27/1443 ,  H04Q3/521

摘要： A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.

摘要翻译： 一种PNPN半导体开关，包括N型半导体衬底，形成在N型衬底的表面上的间隔开的第一和第二P型扩散区域，形成在第二P型扩散区域中的间隔开的第一和第二N型扩散区域，第一 栅极绝缘层，形成在第一和第二N型扩散区域之间的第二P型扩散区域的表面上以覆盖其部分;形成在第一和第二N型扩散区域之间的第一栅极绝缘层上的第一栅电极， 电阻区域，设置在所述第一栅极绝缘层上，所述电阻区域的与所述第一栅极电极相反一侧的一端，覆盖所述第一栅电极和所述电阻区域的第二栅极绝缘层，形成在所述第一栅极绝缘层的表面上的半绝缘层 基板除了第一和第二P型扩散区域之外，覆盖半绝缘层的绝缘层，P栅极电极 与第二P型扩散区域和第二N型扩散区域连接的第二栅电极，形成在第一栅极电极上方的第二栅极绝缘层上的第二栅电极，连接到第一N型扩散区域的阴极电极， 连接到第一P型扩散区域和第二栅电极的阳极电极和形成在第一栅极绝缘层正下方以及第一和第二N型扩散区域之间的高电阻区域。

公开(公告)号：US4649414A

公开(公告)日：1987-03-10

申请号：US778164

申请日：1985-09-18

申请人： Jun Ueda ,  Hirokazu Tsukada ,  Yoichi Nanba

发明人： Jun Ueda ,  Hirokazu Tsukada ,  Yoichi Nanba

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/43 ,  H01L29/74 ,  H01L29/749 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L29/435 ,  H01L29/7436 ,  H01L29/7813

摘要： In a planer type PNPN semiconductor switch having a MOS FET structure, a field plate electrode is embedded in an insulator covering a surface of a semiconductor substrate to overlie an interface between the semiconductor substrate and a P gate region for limiting an extention of a depletion layer from an anode region to a P gate region.

摘要翻译： 在具有MOS FET结构的平面型PNPN半导体开关中，场板电极嵌入在覆盖半导体衬底的表面的绝缘体中，以覆盖半导体衬底和P栅极区之间的界面，以限制耗尽层的扩展 从阳极区到P栅区。