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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20110079834A1

    公开(公告)日：2011-04-07

    申请号：US12896233

    申请日：2010-10-01

    申请人： Masayuki YANAGISAWA ,  Hiroshi Furuta ,  Hiroyasu Kitajima ,  Katsuya Izumi

    发明人： Masayuki YANAGISAWA ,  Hiroshi Furuta ,  Hiroyasu Kitajima ,  Katsuya Izumi

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11509 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers.

    摘要翻译： 半导体集成电路器件具有：具有源极/漏极扩散层的MISFET; 分别连接到源极/漏极扩散层的第一插头; 通过所述第一插塞连接到所述源/漏扩散层中的一个的第一互连; 通过所述第一插头电连接到所述源/漏扩散层中的另一个的第二插头; 连接到第二插头的第二互连; 以及位于MISFET的栅电极上方的电容器电极。 第一互连不形成在下电容器电极的上方，而第二互连形成在上电容器电极上方。 在源/漏扩散层之一的上部位置处不设置连接第一互连和另一互连的插头。 第一互连不设置在另一个源极/漏极扩散层的上部位置。

    Semiconductor integrated circuit device and dummy pattern arrangement method
    6.
    发明授权
    Semiconductor integrated circuit device and dummy pattern arrangement method 失效
    半导体集成电路器件和虚拟图案布置方法

    公开(公告)号：US07772070B2

    公开(公告)日：2010-08-10

    申请号：US11711783

    申请日：2007-02-28

    申请人： Hiroyasu Kitajima ,  Hiroshi Furuta ,  Toshikatsu Jinbo

    发明人： Hiroyasu Kitajima ,  Hiroshi Furuta ,  Toshikatsu Jinbo

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/092 ,  H01L27/0207 ,  H01L29/78

    摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

    摘要翻译： 根据本发明实施例的半导体集成电路器件包括功能电路区域，该功能电路区域包括功能电路，在功能电路区域以外的区域中形成的虚拟区域，以及形成在虚拟区域中并具有虚拟区域的多个虚设MOSFET 在虚拟扩散层上形成栅电极，所述多个虚设MOSFET被配置为使得在预定部分中虚拟扩散层和伪栅电极的日期速率保持恒定。

    Semiconductor device and method of manufacturing the same
    7.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20100032740A1

    公开(公告)日：2010-02-11

    申请号：US12458335

    申请日：2009-07-08

    申请人： Hiroyasu Kitajima

    发明人： Hiroyasu Kitajima

    IPC分类号： H01L27/108 ,  H01L21/02

    CPC分类号： H01L27/0207 ,  H01L23/5258 ,  H01L27/10814 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device that enables placement of a line or the like under a fuse without any additional step and a method of manufacturing the same are provided. The semiconductor device includes a plurality of first capacitor holes made in an insulating layer, a capacitor formed in the first capacitor holes, a DRAM cell made up of the capacitor and a transistor coupled to the capacitor, a plurality of second capacitor holes made in the insulating layer, and a fuse formed between the second capacitor holes.

    摘要翻译： 提供了一种使得能够在没有任何附加步骤的情况下将线路等放置在保险丝下方的半导体器件及其制造方法。 半导体器件包括：绝缘层中形成的多个第一电容器孔，形成在第一电容器孔中的电容器，由电容器构成的DRAM单元和耦合到电容器的晶体管;多个第二电容器孔， 绝缘层和形成在第二电容器孔之间的熔丝。

    Semiconductor integrated circuit device and dummy pattern arrangement method
    8.
    发明申请
    Semiconductor integrated circuit device and dummy pattern arrangement method 失效
    半导体集成电路器件和虚拟图案布置方法

    公开(公告)号：US20070221957A1

    公开(公告)日：2007-09-27

    申请号：US11711783

    申请日：2007-02-28

    申请人： Hiroyasu Kitajima ,  Hiroshi Furuta ,  Toshikatsu Jinbo

    发明人： Hiroyasu Kitajima ,  Hiroshi Furuta ,  Toshikatsu Jinbo

    IPC分类号： H01L27/10

    CPC分类号： H01L27/092 ,  H01L27/0207 ,  H01L29/78

    摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

    摘要翻译： 根据本发明实施例的半导体集成电路器件包括功能电路区域，该功能电路区域包括功能电路，在功能电路区域以外的区域中形成的虚拟区域，以及形成在虚拟区域中并具有虚拟区域的多个虚设MOSFET 在虚拟扩散层12上形成栅电极，多个虚设MOSFET被配置为使得在预定部分中虚拟扩散层和伪栅电极的日期速率保持恒定。