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    Method of forming alignment mark and fabricating semiconductor device
    3.
    发明授权
    Method of forming alignment mark and fabricating semiconductor device 失效
    形成对准标记和制造半导体器件的方法

    公开(公告)号：US5935764A

    公开(公告)日：1999-08-10

    申请号：US997465

    申请日：1997-12-23

    申请人： Eiichiro Kakehashi

    发明人： Eiichiro Kakehashi

    IPC分类号： H01L21/027 ,  G03F7/20 ,  H01L23/544 ,  G03C9/00

    CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002

    摘要： A formation method of an alignment mark is provided. After an etching resist part is formed on a first dielectric layer, a second dielectric layer is formed on the first dielectric layer to cover the etching resist part. Then, the second dielectric layer is selectively etched to form a recess uncovering the etching resists part using a first patterned lithography resist film as a mask. In this etching process, the first dielectric layer is prevented from being etched in the recess of the second dielectric layer by the etching resist part. A layer to be patterned is formed on the second dielectric layer and a second patterned lithography resist film is formed on the layer to be patterned. The second patterned lithography resist film has such a shape that a part of the second lithography resist film is left in the recess of the second dielectric layer. The part of the second lithography resist film in the recess has a height difference approximately equal to or less than the thickness of the second dielectric layer from another part of the second lithography resist film outside the recess. The alignment error of a pattern of the second lithography resist film with respect to a pattern of the second dielectric layer is measured correctly.

    摘要翻译： 提供了一种对准标记的形成方法。 在第一电介质层上形成蚀刻抗蚀剂部分之后，在第一介电层上形成第二介电层以覆盖抗蚀剂部分。 然后，选择性地蚀刻第二电介质层以形成使用第一图案化光刻抗蚀剂膜作为掩模露出抗蚀剂部分的凹部。 在该蚀刻工艺中，防止第一介电层通过抗蚀剂部分在第二介电层的凹部中被蚀刻。 在第二电介质层上形成待图案化的层，并且在待图案化的层上形成第二图案化光刻抗蚀剂膜。 第二图案化光刻抗蚀剂膜具有第二光刻抗蚀剂膜的一部分留在第二介电层的凹部中的形状。 凹部中的第二光刻抗蚀剂膜的一部分具有与凹部外侧的第二光刻抗蚀剂膜的另一部分大致等于或小于第二电介质层的厚度的高度差。 正确地测量第二光刻抗蚀剂膜相对于第二介电层的图案的图案的对准误差。

    Semiconductor memory device and information processing system
    4.
    发明授权
    Semiconductor memory device and information processing system 有权
    半导体存储器件和信息处理系统

    公开(公告)号：US07995373B2

    公开(公告)日：2011-08-09

    申请号：US12549124

    申请日：2009-08-27

    申请人： Kazuhiko Kajigaya ,  Eiichiro Kakehashi

    发明人： Kazuhiko Kajigaya ,  Eiichiro Kakehashi

    IPC分类号： G11C11/24

    CPC分类号： G11C11/404 ,  G11C11/005 ,  G11C11/4076 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32

    摘要： A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is divided into a plurality of areas capable of being designated. The forming controller controls to perform “forming” for the first memory cells in an area selectively designated from the plurality of areas of the memory cell array, and as a result of the forming, the first memory cells are changed to non-volatile second memory cells.

    摘要翻译： 半导体存储器件包括存储单元阵列和成形控制器。 存储单元阵列包括多个第一存储单元，每个第一存储单元具有其中电介质材料夹在两个电极之间的结构，并且存储单元阵列被划分成能够被指定的多个区域。 成形控制器控制对从存储单元阵列的多个区域选择性地指定的区域中的第一存储单元执行“形成”，并且作为形成的结果，第一存储单元被改变为非易失性第二存储器 细胞。