公开(公告)号：US4803530A

公开(公告)日：1989-02-07

申请号：US830868

申请日：1986-02-19

Applicant: Shinji Taguchi ,  Hiroyuki Tango

Inventor： Shinji Taguchi ,  Hiroyuki Tango

IPC: H01L21/8236 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/12 ,  H01L27/0883 ,  H01L29/78657

Abstract: A semiconductor integrated circuit formed on an insulator substrate and comprising a drive transistor and a load transistor, in which a threshold voltage of the load transistor is set in the range of -2.8V to -1.0V so as to ensure stable operation without temperature dependency with respect to working speed and power consumption of the circuit.

Abstract translation: 一种半导体集成电路，其形成在绝缘体基板上并且包括驱动晶体管和负载晶体管，其中负载晶体管的阈值电压设置在-2.8V至-1.0V的范围内，以确保在没有温度依赖性的情况下的稳定运行 关于电路的工作速度和功耗。

公开(公告)号：US4662949A

公开(公告)日：1987-05-05

申请号：US762374

申请日：1985-08-05

Applicant: Tomoyasu Inoue ,  Hiroyuki Tango ,  Kyoichi Suguro ,  Iwao Higashinakagawa ,  Toshihiko Hamasaki

Inventor： Tomoyasu Inoue ,  Hiroyuki Tango ,  Kyoichi Suguro ,  Iwao Higashinakagawa ,  Toshihiko Hamasaki

IPC: H01L21/20 ,  H01L21/263 ,  H01L21/208

CPC classification number: H01L21/2636 ,  H01L21/2022 ,  Y10S148/093

Abstract: In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.

Abstract translation: 在通过用电子束扫描材料区域从非单晶半导体材料形成单晶半导体层的装置中，第一对偏转电极和第二对偏转电极设置在 电子束的路径。 通过用频率低于高频基波信号的调制波信号改变高频基波信号的振幅而产生的偏转信号被提供给第一对的偏转电极。 电极在第一方向上快速偏转电子束，同时改变偏转光束的范围，从而在样品上形成束斑的轨迹。 同时，第二对的偏转电极在第二方向上偏转光束，从而退火材料的区域，以形成单晶半导体层。

公开(公告)号：US4073055A

公开(公告)日：1978-02-14

申请号：US770605

申请日：1977-02-22

Applicant: Minoru Kimura ,  Hiroyuki Tango ,  Yukio Ohmori

Inventor： Minoru Kimura ,  Hiroyuki Tango ,  Yukio Ohmori

IPC: H01L29/78 ,  H01L21/268 ,  H01L21/301 ,  H01L21/304 ,  H01L21/306 ,  H01L21/78 ,  H01L21/86 ,  H01L23/544 ,  H01L27/12 ,  H01L29/786 ,  H01L21/302

CPC classification number: H01L21/3043 ,  H01L21/268 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A method for the manufacture of semiconductor devices comprises the steps of forming a number of mutually electrically isolated semiconductor islands on an insulating substrate and cutting a semiconductor wafer, made of semiconductor elements and substrate, along its dicing line to provide a number of semiconductor chips, the method characterized in that additional semiconductor islands are formed on the insulating substrate simultaneously with, or after, the formation of the first-mentioned semi-conductor islands so that each substantially surrounds the chip. The method permits very easy mask alignments for photoengraving as well as a clear judgment as to whether or not the formation of contact openings has been completed.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在绝缘衬底上形成多个相互电隔离的半导体岛，并沿其切割线切割由半导体元件和衬底制成的半导体晶片以提供多个半导体芯片， 该方法的特征在于，在形成第一提到的半导体岛的同时或之后，在绝缘基板上形成附加的半导体岛，使得其基本上围绕芯片。 该方法允许用于光刻的非常容易的掩模对准以及关于接触开口的形成是否已经完成的明确判断。

公开(公告)号：US4447823A

公开(公告)日：1984-05-08

申请号：US240850

申请日：1981-03-05

Applicant: Kenji Maeguchi ,  Hiroyuki Tango

Inventor： Kenji Maeguchi ,  Hiroyuki Tango

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/86 ,  H01L27/12 ,  H01L29/786 ,  H01L27/02 ,  H01L45/00

CPC classification number: H01L21/86 ,  H01L21/76264 ,  H01L27/12 ,  H01L21/76272 ,  H01L21/76281

Abstract: A semiconductor device having silicon-on-sapphire structure in which a pn junction element is formed in a silicon substrate disposed on a sapphire plate. An oxide layer is formed in the surface area of the p-type region which serves to form the pn junction elements.

Abstract translation: 一种具有硅蓝宝石结构的半导体器件，其中在设置在蓝宝石板上的硅衬底中形成pn结元件。 在用于形成pn结元件的p型区域的表面区域中形成氧化物层。

公开(公告)号：US4080618A

公开(公告)日：1978-03-21

申请号：US720804

申请日：1976-09-07

Applicant: Hiroyuki Tango ,  Tadahiro Takigawa

Inventor： Hiroyuki Tango ,  Tadahiro Takigawa

IPC: H01L21/225 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L23/535 ,  H01L21/2255 ,  H01L29/0847 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90

Abstract: An insulated-gate field-effect transistor having improved high-speed operation characteristics and high channel controllability includes a source region having first and second diffused regions and a drain region having first and second diffused regions. The first diffused regions of both the source and drain regions are formed by diffusion of a first impurity having relatively low diffusion coefficient and the second diffused regions of both the source and drain regions are formed by diffusion of a second impurity having relatively high diffusion coefficient.

Abstract translation: 具有改善的高速操作特性和高通道可控性的绝缘栅场效应晶体管包括具有第一和第二扩散区的源极区和具有第一和第二扩散区的漏极区。 源极和漏极区域的第一扩散区域通过具有相对低扩散系数的第一杂质的扩散而形成，并且源极和漏极区域的第二扩散区域由扩散系数相对较高的第二杂质的扩散形成。

公开(公告)号：US4746803A

公开(公告)日：1988-05-24

申请号：US904942

申请日：1986-09-08

Applicant: Tomoyasu Inoue ,  Hiroyuki Tango ,  Kyoichi Suguro ,  Iwao Higashinakagawa ,  Toshihiko Hamasaki

Inventor： Tomoyasu Inoue ,  Hiroyuki Tango ,  Kyoichi Suguro ,  Iwao Higashinakagawa ,  Toshihiko Hamasaki

IPC: H01L21/20 ,  H01L21/263 ,  H01J3/28 ,  H01L21/26

CPC classification number: H01L21/2636 ,  H01L21/2022 ,  Y10S148/093

Abstract: In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.

Abstract translation: 在通过用电子束扫描材料区域从非单晶半导体材料形成单晶半导体层的装置中，第一对偏转电极和第二对偏转电极设置在 电子束的路径。 通过用频率低于高频基波信号的调制波信号改变高频基波信号的振幅而产生的偏转信号被提供给第一对的偏转电极。 电极在第一方向上快速偏转电子束，同时改变偏转光束的范围，从而在样品上形成束斑的轨迹。 同时，第二对的偏转电极在第二方向上偏转光束，从而退火材料的区域，以形成单晶半导体层。

公开(公告)号：US4288829A

公开(公告)日：1981-09-08

申请号：US951304

申请日：1978-10-13

Applicant: Hiroyuki Tango

Inventor： Hiroyuki Tango

IPC: H03F1/52 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H02H7/20 ,  H03F1/42 ,  H02H3/20

CPC classification number: H02H7/205 ,  H01L27/0251

Abstract: A MOS integrated circuit comprises a MOS IC body including at least one MOS transistor made of an island-like semiconductor layer formed on an insulating substrate, and a protective circuit connected between a signal input terminal and the gate electrode of a MOS transistor at least at an input stage of the MOS IC body and adapted to protect the MOS integrated circuit against an irregular input signal. The protective circuit is also connected between ground and the gate electrode of the MOS transistor at the input stage of the MOS IC body and comprises a protective MOS transistor made of an island-like semiconductor layer formed on the insulating substrate in a manner to be arranged in juxtaposition with the MOS transistor at the input stage of the MOS IC body, a resistor connected between the signal input terminal and the gate circuit of the MOS transistor as the input stage of the MOS IC body the resistor being formed on a grounded insulating layer on the semiconductor layer overlying the insulating substrate to provide a stray capacitance therebetween, the resistor being formed in juxtapositon with the protective MOS transistor.

Abstract translation: MOS集成电路包括：MOS IC体，其包括至少一个MOS晶体管，所述MOS晶体管由形成在绝缘基板上的岛状半导体层构成;以及保护电路，其连接在MOS晶体管的信号输入端和栅极之间，至少在 MOS IC体的输入级，适于保护MOS集成电路不受不规则输入信号的影响。 保护电路也连接在MOS晶体管的输入级的MOS晶体管的接地端和栅电极之间，并且包括由绝缘基板上形成的岛状半导体层构成的保护MOS晶体管， 在MOS IC体的输入级与MOS晶体管并置，连接在信号输入端子和MOS晶体管的栅极电路之间的电阻器作为MOS IC体的输入级，电阻器形成在接地绝缘层上 在覆盖绝缘基板的半导体层上提供杂散电容，电阻器与保护MOS晶体管并置形成。