公开(公告)号：US20130326438A1

公开(公告)日：2013-12-05

申请号：US13530164

申请日：2012-06-22

Applicant: Meng-Xiang LEE ,  Li-Chung HSU ,  Shih-Hsien YANG ,  Ho Che YU ,  King-Ho TAM ,  Chung-Hsing WANG

Inventor： Meng-Xiang LEE ,  Li-Chung HSU ,  Shih-Hsien YANG ,  Ho Che YU ,  King-Ho TAM ,  Chung-Hsing WANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

公开(公告)号：US20110072405A1

公开(公告)日：2011-03-24

申请号：US12831982

申请日：2010-07-07

Applicant: Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207

Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

Abstract translation: 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。

公开(公告)号：US07386823B2

公开(公告)日：2008-06-10

申请号：US11186165

申请日：2005-07-20

Applicant: Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

Inventor： Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic diagram of symbols representing devices forming the pattern. The generator identifies each set of devices in the netlist that exhibits any rule's interconnection pattern as a separate “soft group”, places a constraint consistent with the rule on relative positioning within the schematic diagram of symbols representing the soft group, resolves any constraint conflicts in accordance with a constraint resolution scheme, and then places all device symbols in the schematic diagram in a manner consistent accordance with the constraints.

Abstract translation: 示意图生成器处理网表以基于一组对应于互连设备的单独特征模式的布局规则生成示意图，并且在表示形成该图案的设备的符号的示意图中指定对相对位置的约束。 生成器将网表中的任何规则的互连模式的每组设备识别为单独的“软组”，将表示软组的符号的示意图中的规则与规则相对应的相对定位放置在约束冲突中 根据约束解决方案，然后以符合约束的方式将所有设备符号放置在原理图中。

公开(公告)号：US20070022399A1

公开(公告)日：2007-01-25

申请号：US11186165

申请日：2005-07-20

Applicant: Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

Inventor： Tian-Hau Tsai ,  Po-Hung Lin ,  Shyh-Chang Lin ,  Ho-Che Yu

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A schematic diagram generator processes a netlist or similar circuit description to determine how to place and orient symbols representing devices forming the circuit based on a set of placement rules. Each rule corresponds to a separate characteristic pattern of interconnected devices, and specifies a constraint on relative positioning and/or orientation within the schematic diagram of a set of symbols representing any set of devices forming the corresponding pattern. For each rule, the schematic diagram generator processes the circuit description to identify each set of devices of the electronic circuit exhibiting the rule's corresponding characteristic pattern as a separate “soft group” and establishes a constraint consistent with that rule on relative positioning within the schematic diagram of a set of symbols representing the identified soft group. The schematic diagram generator then resolves any conflicts among the constraints by eliminating some of the constraints and retaining others in accordance with a constraint resolution scheme. The schematic diagram generator thereafter selects positions and orientations within the schematic diagram for all device symbols in a manner consistent with the retained constraints.

Abstract translation: 示意图生成器处理网表或类似电路描述以确定如何基于一组放置规则来放置和定向表示形成电路的装置的符号。 每个规则对应于互连设备的单独的特征模式，并且在表示形成相应模式的任何一组设备的一组符号的示意图中规定了相对定位和/或取向的约束。 对于每个规则，原理图生成器处理电路描述，以将表现出规则相应特征模式的电子电路的每组设备识别为单独的“软组”，并且在原理图中建立与该规则相对于相对定位的约束 表示所识别的软组的一组符号。 原理图生成器然后通过消除一些约束并根据约束解析方案保留其他约束来解决约束之间的任何冲突。 原理图生成器随后以与所保留的约束一致的方式在所有设备符号的示意图中选择位置和取向。

公开(公告)号：US20110035717A1

公开(公告)日：2011-02-10

申请号：US12846594

申请日：2010-07-29

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract translation: 本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。 计算机程序产品具有其上体现计算机程序的介质。 此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和 收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

公开(公告)号：US07739646B2

公开(公告)日：2010-06-15

申请号：US11839042

申请日：2007-08-15

Applicant: Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

Inventor： Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

Abstract translation: 基于计算机的放置和布线（P＆R）工具存储一组电路图案，每个电路图案通过参考设备组的每个设备并通过指示通过网络将形成被引用设备的设备元件相互连接来描述单独的设备组，一组 布置图案，每个提供用于放置形成由对应的一个电路图案描述的设备组的IC设备元件和一组路由样式的引导件，以用作在放置在特定图案中的设备元件之间布线网络的引导。 为了产生由网表描述的模拟IC的布局，P＆R工具识别IC中的每组设备，形成由任何电路图形描述的设备组。 然后，P＆R工具为每个识别的设备组生成单独的设备组布局，使用放置模式作为在设备组布局中放置设备元素的引导，并使用路由样式作为在设备组布局中互连设备元素的路由网络的引导。 P＆R工具还为未包含在任何识别的设备组中的每个设备生成布局。 然后，该工具生成包含每个生成的设备和设备组布局的IC的布局。

公开(公告)号：US09672315B2

公开(公告)日：2017-06-06

申请号：US12846594

申请日：2010-07-29

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

公开(公告)号：US08826195B2

公开(公告)日：2014-09-02

申请号：US13530164

申请日：2012-06-22

Applicant: Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

Inventor： Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

公开(公告)号：US08418117B2

公开(公告)日：2013-04-09

申请号：US12831982

申请日：2010-07-07

Applicant: Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207

Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

Abstract translation: 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。

公开(公告)号：US20080092099A1

公开(公告)日：2008-04-17

申请号：US11839042

申请日：2007-08-15

Applicant: Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

Inventor： Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

Abstract translation: 基于计算机的放置和布线（P＆R）工具存储一组电路图案，每个电路图案通过参考设备组的每个设备并通过指示通过网络将形成被引用设备的设备元件相互连接来描述单独的设备组，一组 布置图案，每个提供用于放置形成由对应的一个电路图案描述的设备组的IC设备元件和一组路由样式的引导件，以用作在放置在特定图案中的设备元件之间布线网络的引导。 为了产生由网表描述的模拟IC的布局，P＆R工具识别IC中的每组设备，形成由任何电路图形描述的设备组。 然后，P＆R工具为每个识别的设备组生成单独的设备组布局，使用放置模式作为在设备组布局中放置设备元素的引导，并使用路由样式作为在设备组布局中互连设备元素的路由网络的引导。 P＆R工具还为未包含在任何识别的设备组中的每个设备生成布局。 然后，该工具生成包含每个生成的设备和设备组布局的IC的布局。