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    System for terminating high speed input/output buffers in an automatic test equipment environment to enable external loopback testing
    3.
    发明授权
    System for terminating high speed input/output buffers in an automatic test equipment environment to enable external loopback testing 失效
    用于在自动测试设备环境中终止高速输入/输出缓冲器的系统，以实现外部环回测试

    公开(公告)号：US08098073B2

    公开(公告)日：2012-01-17

    申请号：US11862451

    申请日：2007-09-27

    申请人： Derrick Sai-Tang Butt ,  Hong-Him Lim ,  David Carkeek

    发明人： Derrick Sai-Tang Butt ,  Hong-Him Lim ,  David Carkeek

    IPC分类号： G01R31/02

    CPC分类号： G01R31/31716 ,  G01R31/31905 ,  G01R31/31926

    摘要： An apparatus comprising a test termination card having a first set of connections and a second set of connections. The first set of connections may be configured to connect to a specific pinout of a device under test. The second set of connections may be configured to connect to a general pinout of a tester load board. The termination card may toggle between (a) connecting the first set of connectors to the second set of connectors to implement a first test type and (b) disconnecting the first set of connectors from the second set of connectors to implement a second test type.

    摘要翻译： 一种装置，包括具有第一组连接和第二组连接的测试终端卡。 可以将第一组连接配置为连接到被测设备的特定引脚分布。 第二组连接可以被配置为连接到测试仪负载板的通用引脚。 终端卡可以在（a）将第一组连接器连接到第二组连接器之间切换以实现第一测试类型，并且（b）将第一组连接器与第二组连接器断开连接，以实现第二测试类型。

    Apparatus and methods for improved input/output cells
    5.
    发明授权
    Apparatus and methods for improved input/output cells 有权
    改进输入/输出单元的装置和方法

    公开(公告)号：US07239170B2

    公开(公告)日：2007-07-03

    申请号：US10614956

    申请日：2003-07-08

    申请人： Victor Suen ,  William Lau ,  Hong-Him Lim ,  Cheng-Gang Kong

    发明人： Victor Suen ,  William Lau ,  Hong-Him Lim ,  Cheng-Gang Kong

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093

    摘要： Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

    摘要翻译： 提供了用于改善诸如存储器控制器和RLDRAM之类的电子设备之间的数据交换的装置和方法。 I / O单元包括用于将第一信号传送到与其耦合的电子设备并用于从电子设备接收第二信号的信号焊盘。 在一个方面，占空比控制器耦合到信号焊盘，用于平衡相对于时钟信号的第一信号的占空比。 在另一方面，当I / O单元正在接收第二信号时，动态可切换端接耦合到信号焊盘以提供终端阻抗。

    Apparatus and methods for improved input/output cells
    6.
    发明申请
    Apparatus and methods for improved input/output cells 有权
    改进输入/输出单元的装置和方法

    公开(公告)号：US20050010833A1

    公开(公告)日：2005-01-13

    申请号：US10614956

    申请日：2003-07-08

    申请人： Victor Suen ,  William Lau ,  Hong-Him Lim ,  Cheng-Gang Kong

    发明人： Victor Suen ,  William Lau ,  Hong-Him Lim ,  Cheng-Gang Kong

    IPC分类号： G06F1/04 ,  G11C7/10

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093

    摘要： Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

    摘要翻译： 提供了用于改善诸如存储器控制器和RLDRAM之类的电子设备之间的数据交换的装置和方法。 I / O单元包括用于将第一信号传送到与其耦合的电子设备并用于从电子设备接收第二信号的信号焊盘。 在一个方面，占空比控制器耦合到信号焊盘，用于平衡第一信号相对于时钟信号的占空比。 在另一方面，当I / O单元正在接收第二信号时，动态可切换终端耦合到信号焊盘以提供终端阻抗。