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    Generic low power strobe based system and method for interfacing memory controller and source synchronous memory
    1.
    发明授权
    Generic low power strobe based system and method for interfacing memory controller and source synchronous memory 有权
    基于通用低功率选通的系统和接口存储器控制器和源同步存储器的方法

    公开(公告)号：US08743634B2

    公开(公告)日：2014-06-03

    申请号：US13016071

    申请日：2011-01-28

    Applicant: Terence J. Magee ,  Cheng-Gang Kong

    Inventor： Terence J. Magee ,  Cheng-Gang Kong

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.

    Abstract translation: 一种用于使用通用低功率选通器来连接存储器控制器和源同步存储器的系统和方法。 可以通过选通连续的双速率时钟来生成一组双倍速率（2×）选通脉冲，以便仅在从控制器到存储器的数据传输的持续时间内使能一组双速率选通。 SDR连续单速率（1×）时钟域相对于存储器控制器的数据和控制可通过采用一组双速率选通进行采样，移动到一组双速率时钟域。 双速率选通组的相位可以相对于连续单速率时钟移位，并且可以通过改变一组双速率选通的相位来动态地切换所产生的同步信号与存储器的相位关系。 双速率时钟域的集合使每个位片被独立编程，以在相对于控制器单速率时钟的每个相位处产生到存储器的输出。

    Method and computer program for generating grounded shielding wires for signal wiring
    2.
    发明授权
    Method and computer program for generating grounded shielding wires for signal wiring 失效
    用于生成信号线接地屏蔽线的方法和计算机程序

    公开(公告)号：US08516425B2

    公开(公告)日：2013-08-20

    申请号：US13544632

    申请日：2012-07-09

    Applicant: Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    Inventor： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/84

    Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

    Abstract translation: 提供了一种减少信号偏移的系统和方法。 该方法包括接收具有组件之间的组件和连接的网表。 每个连接具有至少一个信号线。 识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。 对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。 对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

    GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING MEMORY CONTROLLER AND SOURCE SYNCHRONOUS MEMORY
    4.
    发明申请
    GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING MEMORY CONTROLLER AND SOURCE SYNCHRONOUS MEMORY 有权
    一般低功耗基于系统和方法，用于接口存储器控制器和源同步存储器

    公开(公告)号：US20120195141A1

    公开(公告)日：2012-08-02

    申请号：US13016071

    申请日：2011-01-28

    Applicant: Terence J. Magee ,  Cheng-Gang Kong

    Inventor： Terence J. Magee ,  Cheng-Gang Kong

    IPC: G11C7/22

    CPC classification number: G11C7/1072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.

    Abstract translation: 一种用于使用通用低功率选通器来连接存储器控制器和源同步存储器的系统和方法。 可以通过选通连续的双速率时钟来生成一组双倍速率（2×）选通脉冲，以便仅在从控制器到存储器的数据传输的持续时间内使能一组双速率选通。 SDR连续单速率（1×）时钟域相对于存储器控制器的数据和控制可通过采用一组双速率选通进行采样，移动到一组双速率时钟域。 双速率选通组的相位可以相对于连续单速率时钟移位，并且可以通过改变一组双速率选通的相位来动态地切换所产生的同步信号与存储器的相位关系。 双速率时钟域的集合使每个位片被独立编程，以在相对于控制器单速率时钟的每个相位处产生到存储器的输出。

    Signal delay skew reduction system
    5.
    发明授权
    Signal delay skew reduction system 有权
    信号延迟偏差减少系统

    公开(公告)号：US07996804B2

    公开(公告)日：2011-08-09

    申请号：US12015925

    申请日：2008-01-17

    Applicant: Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    Inventor： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/84

    Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

    Abstract translation: 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少相应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。

    Memory interface architecture for maximizing access timing margin
    7.
    发明申请
    Memory interface architecture for maximizing access timing margin 失效
    存储器接口架构，用于最大化访问时序裕量

    公开(公告)号：US20060224847A1

    公开(公告)日：2006-10-05

    申请号：US11097903

    申请日：2005-04-01

    Applicant: Hui-Yin Seto ,  Cheng-Gang Kong

    Inventor： Hui-Yin Seto ,  Cheng-Gang Kong

    IPC: G06F13/00

    CPC classification number: G06F13/1689

    Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

    Abstract translation: 一种包括控制电路，缓冲电路和存储器的装置。 控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

    System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
    8.
    发明授权
    System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses 失效
    在具有相对，绝对，间接和陷阱地址的管道中处理单周期分支指令的系统

    公开(公告)号：US4777587A

    公开(公告)日：1988-10-11

    申请号：US771327

    申请日：1985-08-30

    Applicant: Brian W. Case ,  Rod G. Fleck ,  Cheng-Gang Kong ,  Ole Moller

    Inventor： Brian W. Case ,  Rod G. Fleck ,  Cheng-Gang Kong ,  Ole Moller

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00 ,  G06F9/42

    CPC classification number: G06F9/30058 ,  G06F9/3842

    Abstract: An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

    Abstract translation: 适用于简化指令集计算机的指令处理器采用在单个处理器周期中执行条件分支的指令流水线。 处理器将分支条件视为常规指令操作数，而不是单独条件代码寄存器中的特殊情况。 条件位和分支目标地址确定要获取哪个指令，分支在执行下一条指令之前不起作用。 以这种方式，不需要在流水线中物理地跟随分支指令的指令的替换，并且分支发生在分配给它的流水线的单个周期内。 一个简单的电路实现这种延迟分支方法。 结合处理器的计算机容易地执行用于子程序，中断和陷阱的调用的特殊处理技术。

    Memory interface architecture for maximizing access timing margin
    10.
    发明授权
    Memory interface architecture for maximizing access timing margin 失效
    存储器接口架构，用于最大化访问时序裕量

    公开(公告)号：US08230143B2

    公开(公告)日：2012-07-24

    申请号：US11097903

    申请日：2005-04-01

    Applicant: Hui-Yin Seto ,  Cheng-Gang Kong

    Inventor： Hui-Yin Seto ,  Cheng-Gang Kong

    IPC: G06F13/10

    CPC classification number: G06F13/1689

    Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

    Abstract translation: 一种包括控制电路，缓冲电路和存储器的装置。 控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

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