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    (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
    2.
    发明授权
    (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions 失效
    （k） - 用于并行执行固有顺序指令的一次性流水线处理器

    公开(公告)号：US4594655A

    公开(公告)日：1986-06-10

    申请号：US475286

    申请日：1983-03-14

    申请人： Hsieh T. Hao ,  Huei Ling ,  Howard E. Sachar ,  Jeffrey Weiss ,  Yannis J. Yamour

    发明人： Hsieh T. Hao ,  Huei Ling ,  Howard E. Sachar ,  Jeffrey Weiss ,  Yannis J. Yamour

    IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F7/42

    CPC分类号： G06F9/3889 ,  G06F9/3853

    摘要： Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

    摘要翻译： 为具有附加功能的二次数据流设施提供模拟，以便为某些操作模拟先决条件指令和相关指令的同时处理，通过消除延迟时间来显着提高固有顺序指令（k）的同时流水线处理 计算先决条件操作数。 例如，指令A + B = Z1后跟指令Z1 + C = Z2是固有顺序的，A + B = Z1是先决条件指令，Z1 + C = Z2是相关指令。 专门设备的二次数据流设备不等待来自前提指令的表观输入操作数Z1， 它模拟Z1，而与A + B = Z1并行执行A + B + C = Z2。 所有数据流设施不需要为所有指令设备齐全; 辅助数据流设施通常可能不如初级数据流设施那么庞大，但在诸如加法器的关键器官中更复杂。 二次数据流设施的三输入加法器模拟主数据流设施的双输入加法器的结果，同时发生在双输入主数据流设备加法器中，将第三操作数与仿真结果相加，而没有 延迟。 指令单元正常地解码指令序列以控制（k）一次执行，其中没有指令互锁或依赖; 延迟依赖指令的执行，直到操作数变得可用; 并且通过使用辅助数据流设施的附加能力来模拟先决操作数，在有限数量的情况下恢复（k）一次执行。 控制单元执行内务处理以执行指令。

    Method and system for recapturing a trajectory of an object
    5.
    发明授权
    Method and system for recapturing a trajectory of an object 有权
    用于重新捕获物体轨迹的方法和系统

    公开(公告)号：US06449382B1

    公开(公告)日：2002-09-10

    申请号：US09300999

    申请日：1999-04-28

    申请人： Arthur Charles Ciccolo ,  Philip C. D. Hobbs ,  Howard E. Sachar

    发明人： Arthur Charles Ciccolo ,  Philip C. D. Hobbs ,  Howard E. Sachar

    IPC分类号： G06K900

    CPC分类号： G06K9/32 ,  G06K9/209 ,  G06T7/292 ,  G06T2207/30241

    摘要： The present invention is in the field of sensor fusion, and discloses in one embodiment a method for extracting the trajectories of moving objects from an assembly of low-resolution sensors, whose spatial relationships are initially unknown, except that their fields of view are known to overlap so as to form a continuous coverage region, which may be much larger than the field of view of any individual sensor. Segments of object trajectories may be extracted from the data of each sensor, and then stitched together to reconstruct the trajectories of the objects. The stitching process also allows determination of the spatial relationships between the sensors, so that from initially knowing little or nothing about the sensor arrangement or the paths of the objects, both may be reconstructed unambiguously.

    摘要翻译： 本发明在传感器融合领域，并且在一个实施例中公开了一种用于从空间关系最初未知的低分辨率传感器的组件中提取移动物体的轨迹的方法，除了它们的视野已知 重叠以便形成连续的覆盖区域，其可以比任何单个传感器的视场大得多。 可以从每个传感器的数据中提取物体轨迹的部分，然后缝合在一起以重建对象的轨迹。 缝合过程还允许确定传感器之间的空间关系，使得从关于传感器布置或物体的路径的初步了解很少或没有知道，两者可以被明确地重建。

    Decode history table for conditional branch instructions
    8.
    发明授权
    Decode history table for conditional branch instructions 失效
    解码条件分支指令的历史表

    公开(公告)号：US4477872A

    公开(公告)日：1984-10-16

    申请号：US339561

    申请日：1982-01-15

    申请人： Jacques J. Losq ,  Gururaj S. Rao ,  Howard E. Sachar

    发明人： Jacques J. Losq ,  Gururaj S. Rao ,  Howard E. Sachar

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： A method and apparatus predicting the outcome of a conditional branch instruction based on the previous performance of the branch, rather than on the instruction fields. The prediction of the outcome of a conditional branch instruction is performed utilizing a table that records the history of the outcome of the branch at a given memory location. A decode-time history table (DHT) is utilized. The DHT attempts to guess only the outcome of a conditional branch instruction, but not its target address. Thus, it can only be used to guess the branch outcomes at decode time when the target address is available. During the decoding of a conditional branch instruction, a table is accessed using the memory address of the branch instruction itself or some portions thereof. The table records the history of the outcomes of the branch at this memory location up to the congruence of the table size. A combinational circuit determines the guess (taken or not taken) from the branch history as provided by the table.

    摘要翻译： 一种方法和装置，其基于分支的先前性能而不是指令字段来预测条件分支指令的结果。 使用在给定存储器位置记录分支的结果的历史的表来执行条件分支指令的结果的预测。 使用解码时间历史表（DHT）。 DHT尝试仅猜测条件分支指令的结果，而不是其目标地址。 因此，当目标地址可用时，它只能用于在解码时猜测分支结果。 在条件转移指令的解码期间，使用分支指令本身的存储器地址或其某些部分访问表。 该表记录了该记录位置上分支结果的历史记录，直到表格大小一致。 组合电路确定从表中提供的分支历史中的猜测（取或未采用）。