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1.发明授权Structure and method to reduce wafer warp for gallium nitride on silicon wafer 有权减少硅晶片上氮化镓晶片翘曲的结构和方法公开(公告)号：US08629531B2
公开(公告)日：2014-01-14
申请号：US13030645
申请日：2011-02-18
申请人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
CPC分类号： H01L29/7787 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L29/0649 , H01L29/107 , H01L29/2003 , H01L29/66462 , H01L33/007 , H01L33/12
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.
摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。
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2.发明申请STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER 有权减少氮化硅在硅胶上的波纹的结构和方法公开(公告)号：US20120211759A1
公开(公告)日：2012-08-23
申请号：US13030645
申请日：2011-02-18
申请人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
CPC分类号： H01L29/7787 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L29/0649 , H01L29/107 , H01L29/2003 , H01L29/66462 , H01L33/007 , H01L33/12
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.
摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。
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