公开(公告)号：US20110284936A1

公开(公告)日：2011-11-24

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/772 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。