公开(公告)号：US08564102B2

公开(公告)日：2013-10-22

申请号：US13108231

申请日：2011-05-16

申请人： Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

发明人： Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

摘要翻译： 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

申请人： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

发明人： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC分类号： C25B15/00 ,  C25B9/00

CPC分类号： C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

摘要： An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

摘要翻译： 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US20090305502A1

公开(公告)日：2009-12-10

申请号：US12476793

申请日：2009-06-02

申请人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

发明人： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割的凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US07544538B2

公开(公告)日：2009-06-09

申请号：US11775120

申请日：2007-07-09

申请人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

摘要： Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

摘要翻译： 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20080157287A1

公开(公告)日：2008-07-03

申请号：US12003798

申请日：2008-01-02

申请人： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

发明人： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

摘要翻译： 提供半导体器件及其形成方法。 所述方法可以包括在初步半导体衬底中形成孔，在初步半导体衬底的孔中形成绝缘层，在绝缘层和初级半导体衬底上形成电镀导电层，形成与电镀导电性接触的晶种金属层 层，并且生长种子金属层以形成穿硅通孔（TSV）。 TSV可以通过电镀工艺形成，使得种子金属层从孔的下部生长到孔的上部。

公开(公告)号：US20080141933A1

公开(公告)日：2008-06-19

申请号：US11984402

申请日：2007-11-16

申请人： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

发明人： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

IPC分类号： B05C5/00

CPC分类号： C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885

摘要： Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.

摘要翻译： 提供了一种用于对具有期望层的半导体物体进行电镀的半导体电镀系统。 半导体电镀系统包括：电镀槽，其配置为容纳用于电镀半导体物体的电镀液;以及电镀液感应装置，其被配置为使电镀液向半导体物体螺旋状流动。

公开(公告)号：US20070176240A1

公开(公告)日：2007-08-02

申请号：US11556931

申请日：2006-11-06

申请人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

发明人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

IPC分类号： H01L23/62

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4813 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

摘要翻译： 形成连接到半导体芯片的焊盘的导线结构的方法包括在半导体芯片的有源表面上沉积钝化层，在焊盘和钝化层上沉积种子金属层，在金属层上沉积金属层 种子金属层，蚀刻种子金属层的选定部分，留下未蚀刻的第一区域，与接合焊盘重叠，第二区域与连接焊盘重叠，其中线结构由金属层电连接到接合焊盘， 连接焊盘，但是从钝化层浮起，并且在导线结构上沉积绝缘层。

公开(公告)号：US20170110445A1

公开(公告)日：2017-04-20

申请号：US15391424

申请日：2016-12-27

申请人： PIL-KYU KANG ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  JU-IL CHOI ,  Yi Koan Hong

发明人： PIL-KYU KANG ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  JU-IL CHOI ,  Yi Koan Hong

IPC分类号： H01L25/00 ,  H01L21/304 ,  H01L23/48 ,  H01L25/065 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

公开(公告)号：US20160086874A1

公开(公告)日：2016-03-24

申请号：US14858572

申请日：2015-09-18

申请人： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

发明人： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047

摘要： A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

摘要翻译： 半导体器件可以包括具有表面的衬底。 通孔结构可以延伸穿过衬底朝向衬底的表面，其中通孔结构包括上表面。 衬垫结构可以在衬底的表面上，其中衬垫结构可以包括具有至少一个突起的下表面，其被配置为朝向通孔结构的上表面突出。

公开(公告)号：US08482129B2

公开(公告)日：2013-07-09

申请号：US13027594

申请日：2011-02-15

申请人： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

发明人： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

摘要： A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

摘要翻译： 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。