公开(公告)号：US09694887B2

公开(公告)日：2017-07-04

申请号：US14126801

申请日：2011-09-23

申请人： Jin Suk Lee ,  Ji Nam Kim ,  Hyun Sang Park ,  Hyung Gil Park ,  Kwang Jun Paik ,  Dong Hyun Lee ,  Tae Goo Lee ,  Sung Wook Chung ,  Tetsuji Hoshino ,  Jong Soo Seo ,  Seung Myun Hwangbo

发明人： Jin Suk Lee ,  Ji Nam Kim ,  Hyun Sang Park ,  Hyung Gil Park ,  Kwang Jun Paik ,  Dong Hyun Lee ,  Tae Goo Lee ,  Sung Wook Chung ,  Tetsuji Hoshino ,  Jong Soo Seo ,  Seung Myun Hwangbo

IPC分类号： B63H5/10 ,  B63H23/02 ,  B63H5/14 ,  B63H1/04 ,  B63H21/12 ,  B63H5/125 ,  B63H21/38 ,  B63H23/06 ,  B63H23/32

CPC分类号： B63H5/10 ,  B63H1/04 ,  B63H5/125 ,  B63H5/14 ,  B63H21/12 ,  B63H21/386 ,  B63H23/02 ,  B63H23/321 ,  B63H2005/103 ,  B63H2005/106 ,  B63H2005/1258 ,  B63H2023/0283 ,  B63H2023/067 ,  B63H2023/323

摘要： Disclosed are a propulsion device for a ship and a ship having same. The propulsion device, according to an embodiment of the present invention, comprises: a rear propeller fixed to a driveshaft; a front propeller positioned in front of the rear propeller, and supported rotably on the driveshaft; and a counter rotation device for reversing and transmitting the rotation of the driveshaft to the front propeller; a motor for rotating the driveshaft; and an housing, which extends from to the lower part of the hull, and which is installed so as to envelope the counter rotation device and the motor.

公开(公告)号：US20160071455A1

公开(公告)日：2016-03-10

申请号：US14743044

申请日：2015-06-18

申请人： Hye-Jin JUNG ,  Hyun-Sang PARK ,  Kyung-Chun KIM

发明人： Hye-Jin JUNG ,  Hyun-Sang PARK ,  Kyung-Chun KIM

IPC分类号： G09G3/20

CPC分类号： G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0452 ,  G09G2310/0248 ,  G09G2310/0254 ,  G09G2310/0256 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2310/066 ,  G09G2330/023

摘要： A display driver and display method are provided. The display driver includes a line buffer which receives a plurality of first pixel data corresponding to a first line, and a controller which receives a plurality of second pixel data corresponding to a second line that is different from the first line. The controller also receives the first pixel data from the line buffer, classifies the second pixel data into a plurality of transition types based on the first pixel data and the second pixel data, calculates one or more characteristic values indicating characteristics of each transition type, and determines whether to perform charge sharing of channels based on the characteristic values.

摘要翻译： 提供显示驱动器和显示方法。 显示驱动器包括接收与第一行对应的多个第一像素数据的行缓冲器，以及接收与第一行不同的第二行对应的多个第二像素数据的控制器。 所述控制器还从所述行缓冲器接收所述第一像素数据，基于所述第一像素数据和所述第二像素数据将所述第二像素数据分类为多个转换类型，计算表示每个转换类型的特征的一个或多个特征值，以及 基于特征值确定是否进行信道的电荷共享。

公开(公告)号：US08976097B2

公开(公告)日：2015-03-10

申请号：US13600739

申请日：2012-08-31

申请人： Woo-nyoung Lee ,  Hyun-sang Park ,  Seong-young Ryu

发明人： Woo-nyoung Lee ,  Hyun-sang Park ,  Seong-young Ryu

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3696

摘要： A driving apparatus and a display driving system. The driving apparatus includes a first amplification unit receiving a first signal and outputting a driving signal of a positive polarity voltage with respect to a reference voltage, a second amplification unit receiving a second signal and outputting a driving signal of a negative polarity voltage with respect to the reference voltage, and a controller for determining a chopping signal applied to a chopping terminal of the second amplification unit such that an offset polarity of an output voltage of the first amplification unit and an offset polarity of an output voltage of the second amplification unit are the same.

摘要翻译： 驱动装置和显示驱动系统。 所述驱动装置包括：第一放大单元，接收第一信号并输出​​相对于参考电压的正极性电压的驱动信号;第二放大单元，接收第二信号，并输出负极性电压的驱动信号相对于 参考电压和用于确定施加到第二放大单元的斩波端的斩波信号的控制器，使得第一放大单元的输出电压的偏移极性和第二放大单元的输出电压的偏移极性为 一样。

公开(公告)号：US20120169783A1

公开(公告)日：2012-07-05

申请号：US13292360

申请日：2011-11-09

申请人： Hyun-sang Park

发明人： Hyun-sang Park

IPC分类号： G09G5/10

CPC分类号： G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/023

摘要： A display driving circuit includes a buffer unit receiving gradation voltages and generating data signals that drive a panel. A first buffer unit includes “M” main buffers corresponding to M data lines of the panel and a second buffer unit comprises “N” sub buffers, N being less than M. A first switch unit controls a transmission path along which the gradation voltages are applied to the buffer unit, and a second switch unit controls a transmission path along which the data signals are supplied to the data lines. Switches in the second switch unit are turned ON during charge sharing.

摘要翻译： 显示驱动电路包括接收灰度电压并产生驱动面板的数据信号的缓冲单元。 第一缓冲单元包括对应于面板的M条数据线的“M”个主缓冲器，第二缓冲单元包括N个小于M的“N”个子缓冲器。第一开关单元控制灰度电压为 施加到缓冲单元，第二开关单元控制向数据线提供数据信号的传输路径。 电荷共享时，第二开关单元中的开关导通。

公开(公告)号：US20110283042A1

公开(公告)日：2011-11-17

申请号：US13067071

申请日：2011-05-05

申请人： Young-Sun Jeon ,  Ho Jin Lee ,  Joon Hyuk Cha ,  Shi Hwa Lee ,  Young Su Moon ,  Hyun Sang Park

发明人： Young-Sun Jeon ,  Ho Jin Lee ,  Joon Hyuk Cha ,  Shi Hwa Lee ,  Young Su Moon ,  Hyun Sang Park

IPC分类号： G06F12/00

CPC分类号： G06F13/00 ,  G06F13/1647 ,  G06F15/00 ,  G11C7/1042

摘要： A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks.

摘要翻译： 提供了一种事务分割装置和方法，其中访问每个存储器中的预定存储体的相邻子事务可以访问不同的存储体。 交易分割装置包括：第一处理单元，用于将交易分为至少一个子交易，所述事务访问包含在存储器中的多个存储体中的第一存储体，以及第二处理单元，用于将至少一个地址 一个子事务，用于使用所述多个存储体来交织所述至少一个子事务。

公开(公告)号：US20100047732A1

公开(公告)日：2010-02-25

申请号：US12523093

申请日：2008-10-06

申请人： Hyun Sang Park

发明人： Hyun Sang Park

IPC分类号： A61C7/00

CPC分类号： A61C7/10 ,  A61C7/00

摘要： Disclosed herein is an apparatus for correcting the position of teeth used in dentistry. The apparatus for correcting the position of teeth is constructed in a structure in which an implantation unit is securely fixed to a palate, e.g., the roof of a mouth, the bony tissue of which is very excellent and the soft tissue thickness of which is small, using a fixing source, opposite suspension parts are suspended by opposite buccal molar areas to draw front teeth backward, whereby the movement of teeth at the molar tooth areas is prevented, and therefore, reimplantation is unnecessary, application points for drawing the front teeth, including the molar teeth, backward are located at the buccal molar areas, whereby the application of a force (a correction force) is easy, it is possible to induce natural extension of a dental arch (an arch-shaped area where teeth are implanted), and the teeth are moved backward to correct the irregularities of teeth, whereby it is possible to considerably reduce a possibility of tooth extraction.

摘要翻译： 本文公开了一种用于校正牙齿中使用的牙齿位置的装置。 用于校正牙齿位置的装置构造成其中植入单元被牢固地固定到腭部的结构，例如口腔的顶部，其骨组织非常优异，并且其软组织厚度小 使用固定源，相对的悬挂部分通过相对的颊摩擦区域悬挂以向前拉前牙，从而防止在摩擦齿区域的齿的移动，因此不需要再植入，用于拉拔前牙的应用点， 包括臼齿，向后位于颊部摩擦区域，由此施加力（矫正力）容易，可以引起牙弓（牙嵌入的弓形区域）的自然延伸， 并且齿向后移动以校正齿的不规则性，由此可以显着降低拔牙的可能性。

公开(公告)号：US20080205781A1

公开(公告)日：2008-08-28

申请号：US12081989

申请日：2008-04-24

申请人： Hyun-sang Park ,  Sun-young Shin

发明人： Hyun-sang Park ,  Sun-young Shin

IPC分类号： G06K9/36 ,  H04N11/04

CPC分类号： H04N1/32475 ,  H04N1/32358 ,  H04N2201/329

摘要： An image processing apparatus for converting image data between a raster format and a block format including an image data processor for providing the image data including a luminance component and at least one chrominance component in the raster format, at least two FIFO memories for storing corresponding image data components, a multiplexer for multiplexing the image data components from the at least two FIFO memories, a line buffer memory for storing outputs of the multiplexer linearly, and an image compressor for receiving the image data components in block format in sequence from the unified line buffer memory and compressing the received image data components. The image processing apparatus may also include an address generator for generating a common read/write address for the line buffer memory; and an image compressor for receiving image data of a v*h block unit from the line memory and compressing the received image data, where when the image data of v lines are read out from the line memory in a block scan order referring to the common read/write address, next image data of v lines are written into the single line memory with reference to the same common read/write address.

摘要翻译： 一种用于在光栅格式和块格式之间转换图像数据的图像处理装置，包括用于提供包括光栅格式的亮度分量和至少一个色度分量的图像数据的图像数据处理器，用于存储对应图像的至少两个FIFO存储器 数据组件，多路复用器，用于多路复用来自至少两个FIFO存储器的图像数据分量;线缓冲存储器，用于存储多路复用器的线性输出;以及图像压缩器，用于从统一线依次接收块格式的图像数据分量 缓冲存储器并压缩接收的图像数据组件。 图像处理装置还可以包括用于生成行缓冲存储器的公共读/写地址的地址发生器; 以及图像压缩器，用于从行存储器接收av * h块单元的图像数据并压缩所接收的图像数据，其中当参考公共读取以块扫描顺序从行存储器读出v行的图像数据时 /写地址，v行的下一图像数据参照相同的公共读/写地址写入单行存储器。

公开(公告)号：US20060140047A1

公开(公告)日：2006-06-29

申请号：US11317131

申请日：2005-12-22

申请人： Hyun-Sang Park ,  Suk-Ki Yoon

发明人： Hyun-Sang Park ,  Suk-Ki Yoon

IPC分类号： G06F3/00 ,  G11C8/00 ,  G06F1/12

CPC分类号： G06F13/4217 ,  G11C7/22

摘要： A self-generated strobe signal generator generates a self-generated strobe signal for a peripheral device using a peripheral device selection signal and a clock signal, without using a conventional strobe signal for all of the peripheral devices. Using the self-generated strobe signal synchronized to the clock signal, a delay time of the conventional strobe signal due to a high fan-out capability requirement and a long path length may be reduced and an operating frequency of an entire system may be improved.

公开(公告)号：US20060133512A1

公开(公告)日：2006-06-22

申请号：US11200015

申请日：2005-08-10

申请人： Hyun-Sang Park

发明人： Hyun-Sang Park

IPC分类号： H04N11/02 ,  H04N11/04 ,  H04N7/12 ,  H04B1/66

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A video decoder and associated methods of operation are disclosed. The video decoder identifies groups of successive not-coded macro-blocks associated with a current frame in a bitstream of compressed video data received from a main memory. The video decoder then reads corresponding groups of macro-blocks associated with a previous frame from a first location in the main memory to a local memory and then back to a second location in the main memory in order to reconstruct the current frame.

摘要翻译： 公开了一种视频解码器和相关的操作方法。 视频解码器识别从主存储器接收的压缩视频数据的比特流中与当前帧相关联的连续未编码宏块的组。 然后，视频解码器从主存储器中的第一位置读取与先前帧相关联的宏块的对应组到本地存储器，然后返回到主存储器中的第二位置，以便重建当前帧。

公开(公告)号：US20060129727A1

公开(公告)日：2006-06-15

申请号：US11200039

申请日：2005-08-10

申请人： Hyun-Sang Park

发明人： Hyun-Sang Park

IPC分类号： G06F13/00

CPC分类号： G06F13/40

摘要： A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to connect the dual master module to a high-speed secondary memory.