公开(公告)号：US06421343B1

公开(公告)日：2002-07-16

申请号：US09137535

申请日：1998-08-21

申请人： Jong Arm Jun ,  Chan Kim ,  Yeong Ho Park ,  Ik Kyun Kim ,  Young Wook Cha ,  Kyou Ho Lee ,  Hyup Jong Kim ,  Jae Geun Kim

发明人： Jong Arm Jun ,  Chan Kim ,  Yeong Ho Park ,  Ik Kyun Kim ,  Young Wook Cha ,  Kyou Ho Lee ,  Hyup Jong Kim ,  Jae Geun Kim

IPC分类号： H04L1228

CPC分类号： H04L12/5601 ,  H04L2012/5612 ,  H04L2012/5616 ,  H04L2012/5653

摘要： An asynchronous transfer mode (ATM) host adapting apparatus comprising: a storage block for storing packet information, received cells, and parameters; an ATM network interface handling block for performing direct memory access of ATM cells and parameter stored therein, segmenting transmit packet information, reassembling received cells, transmitting and receiving the ATM cells to physical media cell received, and arbitrating in the direct memory access; and a secondary interface block for connecting the storage block to the ATM network interface handling block.

摘要翻译： 一种异步传输模式（ATM）主机适配装置，包括：存储分组信息，接收的小区和参数的存储块; 用于执行ATM信元的直接存储器访问和存储在其中的参数的ATM网络接口处理块，分组发送分组信息，重新组合接收到的小区，向所接收的物理介质小区发送和接收ATM信元，并在直接存储器访问中进行仲裁; 以及用于将存储块连接到ATM网络接口处理块的辅助接口块。

公开(公告)号：US06188723B1

公开(公告)日：2001-02-13

申请号：US09112059

申请日：1998-07-09

申请人： Jeong Jin Lee ,  Bong Tae Kim ,  Min Ho Choi ,  Hyup Jong Kim

发明人： Jeong Jin Lee ,  Bong Tae Kim ,  Min Ho Choi ,  Hyup Jong Kim

IPC分类号： H04L2701

CPC分类号： H04L27/34 ,  H04L25/03834

摘要： A finite impulse response (FIR) filter for wave-shaping digital quadrature amplitude modulation (QAM) symbols is disclosed, in which multipliers are replaced with multiplexers, the replaced multiplexers are utilized to receive the symbols directly from a symbol encoder without zero (0) interpolations, and the critical path is reduced by shifting the position of a delay device. The filter includes a first FIR means for delaying the externally inputted symbol data, and for utilizing the delayed symbol data as selection signals to sum up the selected multiplication product (selected from among products obtained by multiplying the symbol values by a pre-set filter tab coefficient) and the selected value selected by a first multiplexing means. A second FIR means delays again the delayed symbol data of the first FIR means, and utilizes the delayed symbol data as selection signals to sum up the selected multiplication product and the output value of the first FIR means.

摘要翻译： 公开了一种用于波形整形数字正交幅度调制（QAM）符号的有限脉冲响应（FIR）滤波器，其中乘法器被多路复用器替代，替换的多路复用器被用于直接从符号编码器接收符号，而不用零（0） 内插，并且通过移动延迟装置的位置来减小关键路径。 滤波器包括用于延迟外部输入的符号数据的第一FIR装置，并且用于利用延迟的符号数据作为选择信号来对所选乘法乘积进行求和（从通过将符号值乘以预设的滤波器选项卡获得的乘积中选择 系数）和由第一多路复用装置选择的选择值。 第二FIR装置再次延迟第一FIR装置的延迟符号数据，并且利用延迟的符号数据作为选择信号来对所选乘法乘积和第一FIR装置的输出值求和。

公开(公告)号：US5859846A

公开(公告)日：1999-01-12

申请号：US685527

申请日：1996-07-24

申请人： Kyeong Soo Kim ,  Hyup Jong Kim

发明人： Kyeong Soo Kim ,  Hyup Jong Kim

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/101 ,  H04L49/106 ,  H04L49/1584 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5605 ,  H04L2012/5626 ,  H04L2012/5674 ,  H04L49/253

摘要： A fully-interconnected ATM switching apparatus comprising a plurality of line interface circuits, each of the line interface circuits including an input port driver for extracting an SDH transmission frame containing cell data with a fixed length and a connection identifier from an input signal, appending a routing tag to the extracted SDH transmission frame and outputting the resultant SDH transmission frame through an input dedicated bus and an output port driver for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier and transferring the resultant SDH transmission frame to an adjacent node, a system clock distributor for generating a clock signal, an initialization controller for controlling system initialization and restart operations, a switch maintenance controller for performing a switch maintenance control operation in response to a network managing cell, a switch call processing controller for performing a call processing operation, a switch module controller for controlling a switching operation, and a plurality of switch output multiplexers for switching cells from the input port drivers to the output port drivers under the control of the switch module controller.

摘要翻译： 一种完全互连的ATM交换设备，包括多个线路接口电路，每个线路接口电路包括用于从输入信号中提取包含固定长度的小区数据和连接标识符的SDH传输帧的输入端口驱动器， 路由标签到所提取的SDH传输帧，并通过输入专用总线输出所得到的SDH传输帧，以及用于从输出专用总线接收信元流的输出端口驱动器，从接收的信元流中移除路由标签，翻译信道标识符 在连接标识符中并将所得到的SDH传输帧传送到相邻节点，用于产生时钟信号的系统时钟分配器，用于控制系统初始化和重新启动操作的初始化控制器，响应于执行开关维护控制操作的开关维护控制器 到网络管理单元， 用于执行呼叫处理操作的瘙痒呼叫处理控制器，用于控制切换操作的开关模块控制器，以及用于在开关模块控制器的控制下将单元从输入端口驱动器切换到输出端口驱动器的多个开关输出多路复用器。

公开(公告)号：US5732085A

公开(公告)日：1998-03-24

申请号：US573093

申请日：1995-12-15

申请人： Kyeong Soo Kim ,  Hyup Jong Kim ,  Keun Bae Kim ,  Jeong Jin Lee

发明人： Kyeong Soo Kim ,  Hyup Jong Kim ,  Keun Bae Kim ,  Jeong Jin Lee

IPC分类号： H04Q11/04 ,  H04J3/24 ,  H04L12/70 ,  H04L12/931 ,  H04L12/937 ,  H04J3/26 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L49/106 ,  H04L49/3081 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04L2012/5684

摘要： The present invention relates to a fixed length packet switching apparatus using multiplexers and demultiplexers in which the apparatus has an output buffer-type construction, protects itself from a temporary overflow occurrence of an output terminal and has the construction of the mutual flow control to enhance its entire performance. The present invention can protect the entire operations as well as enhance the entire performance of the switching apparatus by preventing an obstacle of the switching apparatus due to an overflow temporarily generated from an output terminal, process without a loss of excessive cells a traffic phenomenon of one output port in the switching apparatus, reduce the necessary buffer according to the effect of the rate gain and process smoothly input traffic of the internal buffer having a burst characteristic. Further more, the present invention has a duplicate function of cells able to provide a broadcast-type service distributed to subscribers at one time so that the subscribers can receive a distributed service to thereby increase the effectiveness of the channel.

摘要翻译： 本发明涉及一种使用多路复用器和解复用器的固定长度分组交换设备，其中该设备具有输出缓冲型结构，保护自身免受输出终端的暂时溢出的影响，并且具有相互流控制的结构以增强其 整体表现。 本发明可以通过防止由于从输出端暂时产生的溢出而导致的开关装置的障碍物来提高整个操作的整体性能，而不会损失过多的电池一个交通现象 输出端口，根据速率增益的影响减少必要的缓冲器，并处理具有突发特性的内部缓冲器的平滑输入业务。 此外，本发明具有能够一次提供分配给用户的广播型服务的小区的重复功能，使得用户可以接收分布式服务，从而增加频道的有效性。

公开(公告)号：US06275504B1

公开(公告)日：2001-08-14

申请号：US09138329

申请日：1998-08-24

申请人： Chan Kim ,  Jong Arm Jun ,  Kyou Ho Lee ,  Hyup Jong Kim ,  Jae Geun Kim

发明人： Chan Kim ,  Jong Arm Jun ,  Kyou Ho Lee ,  Hyup Jong Kim ,  Jae Geun Kim

IPC分类号： H04J316

CPC分类号： H04Q11/0478 ,  H04L2012/5652 ,  H04L2012/5674

摘要： A direct memory read and cell transmission apparatus for an ATM cell segmentation system having a host CPU is disclosed. The segmentation circuit of the apparatus transfers the address and size for the start of the DMA by the byte unit. When a predetermined information is provided, and a DMA read is requested, the data is transferred through the bus of the word unit such as the PCI interface, and then necessary bytes are obtained for thereby forming a 32 bit word stream, so that the ATM cell of a 32 bit×12 word form and transfers to the lower circuit. Therefore, when the segmentation circuit processes the buffer, all data are computed by the byte unit, and in an application program, the data are not obtained for transmitting the data to the ATM cell, so that it is possible to enhance the processing capability.

摘要翻译： 公开了一种具有主机CPU的ATM信元分段系统的直接存储器读和单元传输装置。 该设备的分割电路通过字节单位传送DMA开始的地址和大小。 当提供预定的信息并且请求DMA读取时，数据通过诸如PCI接口的字单元的总线传送，然后获得必要的字节，从而形成32位字流，使得ATM 32位x 12字形式的单元，并传输到较低电路。 因此，当分割电路处理缓冲器时，所有数据都通过字节单位计算，并且在应用程序中，不能获得用于将数据发送到ATM信元的数据，从而可以提高处理能力。

公开(公告)号：US5838679A

公开(公告)日：1998-11-17

申请号：US499071

申请日：1995-07-06

申请人： Hyup Jong Kim ,  Kyeong Soo Kim ,  Chan Pak

发明人： Hyup Jong Kim ,  Kyeong Soo Kim ,  Chan Pak

IPC分类号： H04Q3/00 ,  H04L12/801 ,  H04L12/911 ,  H04L12/931 ,  H04Q3/52 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/255 ,  H04L49/258 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5674

摘要： The present invention relates to an Asynchronous Transfer Mode (ATM) multi-channel switch with a structure of grouping/trap/routing that, by designating a port as a group, could accept not only the services having higher speed than the speed of input ports, but also the services having super-rate speed by comprising: an input processing unit for executing reading control of externally inputted cells and adjusting synchronization between an externally inputted cell and a cell returned by blocking and feedback; a channel grouping unit for grouping cells outputted from the input processing unit, according to switching control data; a trapping unit for deciding whether cells grouped in the channel grouping means require switching beyond the capacity of the pertinent channel and, if these cells require switching beyond the capacity of the channel, sending them to the input processing unit by feedback; and a routing unit for routing cells outputted from the trapping unit.

摘要翻译： 本发明涉及具有分组/捕获/路由结构的异步传输模式（ATM）多信道交换机，其通过将端口指定为一组，不仅可以接受具有比输入端口的速度更快的服务 还包括具有超速率的服务，包括：输入处理单元，用于执行外部输入的单元的读取控制，并调整外部输入的单元与通过阻塞和反馈返回的单元之间的同步; 信道分组单元，用于根据切换控制数据对从输入处理单元输出的单元进行分组; 用于确定分组在信道分组装置中的小区是否需要超出相关信道的容量的捕获单元，并且如果这些小区需要超出信道容量的切换，则通过反馈将它们发送到输入处理单元; 以及用于路由从捕获单元输出的小区的路由单元。