公开(公告)号：US12255256B2

公开(公告)日：2025-03-18

申请号：US18376839

申请日：2023-10-05

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/94

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

公开(公告)号：US20240371950A1

公开(公告)日：2024-11-07

申请号：US18774873

申请日：2024-07-16

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor circuit includes a semiconductor substrate, a transistor, and a voltage source. The semiconductor substrate has an original semiconductor surface. The transistor based on the semiconductor substrate includes a gate structure, a channel region, and a first conductive region. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a top surface and a bottom surface, wherein the bottom surface is below the original semiconductor surface. The voltage source, through the semiconductor substrate, is electrically coupled to the transistor from the bottom surface of the first conductive region.

公开(公告)号：US20240363156A1

公开(公告)日：2024-10-31

申请号：US18770651

申请日：2024-07-12

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu ,  Chun Shiah ,  Bor-Doou Rong

IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

公开(公告)号：US12068020B2

公开(公告)日：2024-08-20

申请号：US17574494

申请日：2022-01-12

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu ,  Chun Shiah ,  Bor-Doou Rong

IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

公开(公告)号：US20240105846A1

公开(公告)日：2024-03-28

申请号：US18472233

申请日：2023-09-22

Applicant: Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu ,  Li-Ping HUANG ,  Wen-Hsien Tu

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

公开(公告)号：US20240030347A1

公开(公告)日：2024-01-25

申请号：US18376839

申请日：2023-10-05

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1033

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

公开(公告)号：US20230402457A1

公开(公告)日：2023-12-14

申请号：US18208388

申请日：2023-06-12

Applicant: Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun LU ,  Ming-Hong KUO ,  Chun-Nan LU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0653 ,  H01L29/7833 ,  H01L29/42376 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/66492

Abstract: A transistor structure includes a semiconductor substrate, a gate region a spacer, a first trench, a first isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The first trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The first isolation region is in the first trench. The conductive region is positioned on the first isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.

公开(公告)号：US20230299069A1

公开(公告)日：2023-09-21

申请号：US17952903

申请日：2022-09-26

Applicant: Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun LU ,  Li-Ping HUANG ,  Juang-Ying CHUEH

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/0207 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/42356

Abstract: A standard cell includes plural of transistors including a first type transistor and a second type transistor, plural of contacts coupled to the transistors; at least one input line electrically coupled to the transistors; an output line electrically coupled to the transistors; a VDD contacting line electrically coupled to the transistors; a VSS contacting line electrically coupled to the transistors; wherein the first type transistor includes a first set of fin structures electrically coupled together, the second type transistor includes a second set of fin structures electrically coupled together, and a gap between the first type transistor and the second type transistor is not greater than 3×Fp minus A, wherein Fp is a pitch distance between two adjacent fin structures in the first type transistor and A is a minimum feature size of the standard cell.

公开(公告)号：US20230207645A1

公开(公告)日：2023-06-29

申请号：US18111899

申请日：2023-02-21

Applicant: Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu ,  Li-Ping Huang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/41791 ,  H01L29/785 ,  H01L29/1083 ,  H01L29/7833 ,  H01L29/7835

Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

公开(公告)号：US20230027913A1

公开(公告)日：2023-01-26

申请号：US17813656

申请日：2022-07-20

Applicant: Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun LU ,  Li-Ping HUANG ,  Ming-Hong KUO

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/40

Abstract: A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.