公开(公告)号：US5866938A

公开(公告)日：1999-02-02

申请号：US698349

申请日：1996-08-15

申请人： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

发明人： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

IPC分类号： H01L21/82 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525 ,  H01L29/43 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semi conductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

摘要翻译： 提供具有以下布置的半导体器件。 第一电极形成在半导体衬底的主表面上，并且包括形成在半导体衬底上的第一Al连接层和设置在第一Al连接层上并电连接到第一Al连接层的阻挡金属层，并且用作阻挡 Al。 在半导体衬底上形成绝缘膜以覆盖第一电极。 在绝缘膜上形成开口以使第一电极局部露出。 以部分地覆盖绝缘膜并且与第一电极的阻挡金属层接触的方式形成反熔丝，其间具有开口。 反熔丝由氮/硅原子组成比为0.6〜1.2的氮化硅构成。 第二电极形成在反熔丝薄膜之上，并且包括用作阻挡Al的阻挡金属层。

公开(公告)号：US5550400A

公开(公告)日：1996-08-27

申请号：US270458

申请日：1994-07-05

申请人： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

发明人： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

IPC分类号： H01L21/82 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525 ,  H01L29/43 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

摘要翻译： 提供具有以下布置的半导体器件。 第一电极形成在半导体衬底的主表面上，并且包括形成在半导体衬底上的第一Al连接层和设置在第一Al连接层上并电连接到第一Al连接层的阻挡金属层，并且用作阻挡 Al。 在半导体衬底上形成绝缘膜以覆盖第一电极。 在绝缘膜上形成开口以使第一电极局部露出。 以部分地覆盖绝缘膜并且与第一电极的阻挡金属层接触的方式形成反熔丝，其间具有开口。 反熔丝由氮/硅原子组成比为0.6〜1.2的氮化硅构成。 第二电极形成在反熔丝薄膜之上，并且包括用作阻挡Al的阻挡金属层。

公开(公告)号：US5543334A

公开(公告)日：1996-08-06

申请号：US356419

申请日：1994-12-15

申请人： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

发明人： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  H01L2924/0002

摘要： A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

摘要翻译： 一种半导体器件的屏蔽方法。 制备在栅氧化膜上形成栅电极的硅晶片。 绝缘层沉积在硅晶片上。 待测试的一组晶体管的栅电极部分露出。 在具有暴露的栅电极的硅晶片上沉积导电层。 导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。 用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。 在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。 可以基于测量的电流值来检测栅氧化膜的异常。 筛选方法可以在形成栅电极的完成之前进行。 此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。

公开(公告)号：US08570822B2

公开(公告)日：2013-10-29

申请号：US12978775

申请日：2010-12-27

申请人： Kaoru Hama

发明人： Kaoru Hama

IPC分类号： G11C7/00

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C29/1201

摘要： According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the test data storing memory cells when testing the bit line and makes data to be read out from the read data storing memory cells when reading out the read data.

摘要翻译： 根据实施例，读取电路连接到位线的另一端，用于从存储单元的读取数据读出数据，经由位线存储存储单元的测试数据，读取控制电路使数据被读出 当测试位线时从测试数据存储存储器单元，并且当读出读取的数据时，从读取数据存储存储单元读出数据。

公开(公告)号：US20110228612A1

公开(公告)日：2011-09-22

申请号：US12978775

申请日：2010-12-27

申请人： Kaoru Hama

发明人： Kaoru Hama

IPC分类号： G11C29/02 ,  G11C7/10

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C29/1201

摘要： According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the test data storing memory cells when testing the bit line and makes data to be read out from the read data storing memory cells when reading out the read data.

摘要翻译： 根据实施例，读取电路连接到位线的另一端，用于从存储单元的读取数据读出数据，经由位线存储存储单元的测试数据，读取控制电路使数据被读出 当测试位线时从测试数据存储存储器单元，并且当读出读取的数据时，从读取数据存储存储单元读出数据。

公开(公告)号：US07867671B2

公开(公告)日：2011-01-11

申请号：US11862701

申请日：2007-09-27

申请人： Toshiaki Douzaka ,  Kyosuke Ogawa ,  Kaoru Hama ,  Hiroaki Suzuki

发明人： Toshiaki Douzaka ,  Kyosuke Ogawa ,  Kaoru Hama ,  Hiroaki Suzuki

IPC分类号： G03F1/08 ,  G03F1/14

CPC分类号： G03F1/30 ,  G03F1/70 ,  H01L27/0207

摘要： A photo-mask that includes a first light shielding region which is narrow and elongated, and a second light shielding region which is wider and more elongated than the first light shielding region and is away from the first light shielding region. A phase shifter part and a non-phase shifter part are provided adjacently to both sides of the first light shielding region. Two phase shifter parts or two non-phase shifter parts are respectively provided adjacently to both sides of the second light shielding part.

摘要翻译： 一种光掩模，其包括窄且细长的第一遮光区域，以及比第一遮光区域更宽且更细长且远离第一遮光区域的第二遮光区域。 相邻于第一遮光区域的两侧设置有移相器部件和非移相器部件。 两个相移部件或两个非移相器部分分别设置在第二遮光部分的两侧。

公开(公告)号：US5301146A

公开(公告)日：1994-04-05

申请号：US757273

申请日：1991-09-10

申请人： Kaoru Hama

发明人： Kaoru Hama

IPC分类号： G11C11/41 ,  G11C11/412 ,  G11C11/40

CPC分类号： G11C11/4125

摘要： A memory cell of a static semiconductor memory device includes first and second inverters, first and second variable resistors and first and second transfer transistors. The first variable resistor is connected between an output terminal of the first inverter and an input terminal of the second inverter. The second variable resistor is connected between an output terminal of the second inverter and an input terminal of the first inverter. The first transfer transistor has a current path connected between the output terminal of the first inverter and a first bit line and a gate connected to a word line. The second transfer transistor has a current path connected between the output terminal of the second inverter and a second bit line and a gate connected to the word line. A control circuit controls the resistances of the first and second variable resistors, and the resistances of the first and second variable resistors are controlled to be reduced when a memory cell is selected in the write-in cycle and they are increased when the memory cell is not selected.

摘要翻译： 静态半导体存储器件的存储单元包括第一和第二反相器，第一和第二可变电阻以及第一和第二转移晶体管。 第一可变电阻器连接在第一反相器的输出端和第二反相器的输入端之间。 第二可变电阻器连接在第二反相器的输出端和第一反相器的输入端之间。 第一传输晶体管具有连接在第一反相器的输出端和第一位线之间的电流通路和连接到字线的栅极。 第二传输晶体管具有连接在第二反相器的输出端和第二位线之间的电流通路和连接到字线的栅极。 控制电路控制第一和第二可变电阻器的电阻，并且当在写入周期中选择存储器单元时，第一和第二可变电阻器的电阻被控制为减小，并且当存储器单元是 未选中的。

公开(公告)号：US20120230117A1

公开(公告)日：2012-09-13

申请号：US13233298

申请日：2011-09-15

申请人： Kaoru Hama

发明人： Kaoru Hama

IPC分类号： G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions provided on a substrate and electrically separated from each other, a memory cell block provided in each of the semiconductor regions and includes nonvolatile memory cells, word lines connected to control gates of memory transistors so as to commonly connect memory transistors in a same row, select gate lines connected to gates of select transistors so as to commonly connect select transistors in a same row, and a row decoder configured to apply a first negative voltage to a selected word line from which data is erased, and to apply a second positive voltage to a non-selected word lines from which data is not erased while an erasing voltage is applied to the semiconductor region upon erasing operation.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括设置在基板上并彼此电分离的半导体区域，设置在每个半导体区域中的存储单元块，并且包括非易失性存储单元，连接到存储晶体管的控制栅极的字线 为了共同连接同一行中的存储晶体管，选择连接到选择晶体管的栅极的栅极线，以便共同连接同一行中的选择晶体管，以及行解码器，被配置为将第一负电压施加到所选择的字线 并且在擦除操作时向半导体区域施加擦除电压时，向未被擦除数据的未选择字线施加第二正电压。

公开(公告)号：US5284793A

公开(公告)日：1994-02-08

申请号：US974662

申请日：1992-11-12

申请人： Kaoru Hama

发明人： Kaoru Hama

IPC分类号： H01L21/28 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/225

CPC分类号： H01L21/3115 ,  H01L21/28167 ,  H01L21/76213 ,  H01L21/28211 ,  Y10S438/918 ,  Y10S438/953

摘要： According to this invention, an oxide film is formed on a semiconductor substrate, a metallic boron film or a film containing at least one selected from the group consisting of boron, phosphorus, and arsenic is deposited on the surface of the resultant structure. At least one selected from the group consisting of boron, phosphorus, and arsenic is doped from the metallic boron film or the film containing at least one selected from the group consisting of boron, phosphorus, and arsenic to the oxide film by diffusion without diffusing into the semiconductor substrate. Thus, a semiconductor device having good radiation resistance can be obtained.

摘要翻译： 根据本发明，在半导体衬底上形成氧化物膜，在所得结构的表面上沉积含有选自硼，磷和砷中的至少一种的金属硼膜或膜。 从金属硼膜或含有选自硼，磷和砷中的至少一种的膜，通过扩散将氧化膜中的至少一种掺杂到硼，磷和砷中，而不会扩散到 半导体衬底。 因此，可以获得具有良好的耐辐射性的半导体器件。