公开(公告)号：US06728056B2

公开(公告)日：2004-04-27

申请号：US09683572

申请日：2002-01-21

申请人： Indumini W. Ranmuthu

发明人： Indumini W. Ranmuthu

IPC分类号： G11B503

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/012 ,  G11B5/02 ,  G11B5/3909 ,  G11B2005/0018

摘要： An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current path resistor (160,158), and a biasing circuit (162,164) in series. Each side of the MR head 42 is connected between a respective one of the current path resistors (158,160) and the biasing circuits (162,168). A shunt resistor (170) is connected between the control transistors (154,156) and the current path resistors (158,160) in each of the current paths. When the control transistors (154,156) are not conducting, the current path resistors (158,160) and the shunt resistor (170) shunt the MR head (42).

摘要翻译： 阻抗控制电路（152）跨越MR磁头（42）连接，具有两个电流路径，每个电流路径包括串联的控制晶体管（154,156），电流路径电阻（160,158）和偏置电路（162,164）。 MR头42的每一侧连接在相应的一个电流通路电阻器（158,160）和偏置电路（162,168）之间。 分流电阻器（170）连接在每个电流通路中的控制晶体管（154,156）和电流通路电阻（158,160）之间。 当控制晶体管（154,156）不导通时，电流通路电阻器（158,160）和分流电阻器（170）分流MR磁头（42）。

公开(公告)号：US6016077A

公开(公告)日：2000-01-18

申请号：US199117

申请日：1998-11-24

申请人： Indumini W. Ranmuthu ,  Glenn C. Mayfield

发明人： Indumini W. Ranmuthu ,  Glenn C. Mayfield

IPC分类号： H03F1/08 ,  H03F3/45 ,  H03F1/14 ,  H03F3/16

CPC分类号： H03F1/086

摘要： A method is disclosed for modifying the operational bandwidth of a signal amplification circuit, comprising the steps of providing an amplification circuit for amplifying the electrical signal, providing circuitry to selectably modify capacitive loading within the amplification circuit and coupled to the amplification circuit, and using the circuitry to selectively modify capacitive loading to alter a dominant pole of the amplification circuit, resulting in a modification of the operational bandwidth of the amplification circuit. A user switchable circuit 220 is coupled to an amplification portion (202, 204, 206, 208, 210, 216, 218) of the amplification circuitry such that a user may selectively activate or deactivate the switchable circuitry, effecting a corresponding and balanced increase or decrease of the capacitive loading within the amplification circuitry. The balanced nature of the capacitive loading changes, effected by the user switchable circuitry, provides the advantage of minimizing the effects of common mode noise and instability in the amplifier circuitry.

摘要翻译： 公开了一种用于修改信号放大电路的操作带宽的方法，包括以下步骤：提供用于放大电信号的放大电路，提供可选择地修改放大电路内的电容性负载并耦合到放大电路的电路，并使用 用于选择性地修改容性负载以改变放大电路的主极的电路，导致放大电路的操作带宽的修改。 用户可切换电路220耦合到放大电路的放大部分（202,204,206,208,210,216,218），使得用户可以选择性地启动或停用可切换电路，实现相应和平衡的增加或 降低放大电路内的电容负载。 由用户可切换电路实现的电容负载变化的平衡特性提供了使放大器电路中共模噪声和不稳定性的影响最小化的优点。

公开(公告)号：US08174953B2

公开(公告)日：2012-05-08

申请号：US12622559

申请日：2009-11-20

申请人： Shengyuan Li ,  Indumini W. Ranmuthu ,  Marius V. Dina

发明人： Shengyuan Li ,  Indumini W. Ranmuthu ,  Marius V. Dina

IPC分类号： G11B7/00

CPC分类号： G11B7/126 ,  G11B7/00456

摘要： An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel.

摘要翻译： 描述输入电流通道器件。 该装置包括用于接收参考信号的第一端子; 用于接收第一目标信号的第二终端; 耦合到所述第一终端的通过设备，所述通过设备响应于接收到所述参考信号而用于发送延迟的参考信号; 耦合到所述第一终端和所述第二终端的第一组合逻辑设备，所述第一组合逻辑设备用于响应于接收到所述参考信号和所述第一目标信号而发送第一组合逻辑信号; 耦合用于接收所述延迟参考信号的选择装置，所述第一组合逻辑信号和第一同步信号，所述选择装置用于选择性地发送第二同步信号，并且其中选择性地发送所述第二同步信号减少所述参考信道和 第一个目标通道。

公开(公告)号：US07453659B2

公开(公告)日：2008-11-18

申请号：US11414979

申请日：2006-05-01

申请人： Indumini W. Ranmuthu

发明人： Indumini W. Ranmuthu

IPC分类号： G11B5/02

CPC分类号： G11B5/02 ,  G11B5/022 ,  G11B2005/001

摘要： System and method for write current drivers for inductive heads used in mass storage drives. A preferred embodiment comprises a write current circuit coupled to an inductive write head, a MOS transistor boost circuit and a matching circuit, both coupled to the write current circuit. The write current circuit provides a first current to the inductive write head, while the MOS transistor boost circuit provides a second current for a specified duration to the inductive write head when the MOS transistor boost circuit receives a control signal. The matching circuit selectively decouples a resistive element from the inductive write head when it receives the control signal. The MOS transistor boost circuit can accelerate the transition in a switching of the polarity of the write current and the matching circuit helps to reduce ringing without negatively affecting the speed of the polarity switching by decoupling when the second current is provided.

摘要翻译： 用于大容量存储驱动器中的感应头的写入电流驱动器的系统和方法。 优选实施例包括耦合到感应写入头，MOS晶体管升压电路和匹配电路的写入电流电路，两者都耦合到写入电流电路。 写入电流电路向感性写入头提供第一电流，而MOS晶体管升压电路在MOS晶体管升压电路接收到控制信号时向感应写入头提供规定持续时间的第二电流。 当接收到控制信号时，匹配电路选择性地将电阻元件与感应写入头分离。 MOS晶体管升压电路可以加速写入电流的极性的切换中的转变，并且匹配电路有助于减少振铃，而不会在提供第二电流时通过去耦而极性切换的速度受到影响。

公开(公告)号：US06538832B1

公开(公告)日：2003-03-25

申请号：US09589429

申请日：2000-06-07

申请人： Indumini W. Ranmuthu ,  Hong Jiang

发明人： Indumini W. Ranmuthu ,  Hong Jiang

IPC分类号： G11B509

CPC分类号： H03F3/45991 ,  G11B5/012 ,  G11B5/09 ,  G11B2005/0016 ,  H03F3/45959

摘要： In hard disk drives (HDD), a magnetic read head moves over a portion of the hard disk when reading data. A preamplifier, having an initial amplification stage of the single ended type, connects to the magnetic read head and amplifies a data signal picked up by the magnetic read head. The preamplifier typically has multiple read heads, or channels. In order to reduce noise coming into the read channels of the preamplifier from the substrate capacitances of the input transistors connected to the read heads, the input transistors are grouped together into multiple banks that are multiplexed, or turn on separately. To further aid noise reduction, the poles of the single ended amplifier are matched, that is, the frequency response of the constant voltage side is matched to the frequency response to the signal side. This effectively reduces both ground noise and Vcc power supply noise as the the noise becomes common mode on the inputs to a differential amplifier that is connected to the single ended amplifier. Noise is further minimized by connecting the substrates of the switching transistors connected to the input transistors to magnetic read ground, as opposed to integrated circuit ground.

摘要翻译： 在硬盘驱动器（HDD）中，当读取数据时磁读取头在硬盘的一部分上移动。 具有单端类型的初始放大级的前置放大器连接到磁读头并放大由磁读头读取的数据信号。 前置放大器通常具有多个读取头或通道。 为了减少从连接到读取头的输入晶体管的基板电容进入前置放大器的读取通道的噪声，输入晶体管被分组在多个组中，或分开开启。 为了进一步减少噪声，单端放大器的极点匹配，即恒压侧的频率响应与对信号侧的频率响应相匹配。 由于噪声成为连接到单端放大器的差分放大器的输入上的共模，因此这有效地降低了接地噪声和Vcc电源噪声。 与集成电路接地相反，将连接到输入晶体管的开关晶体管的基板连接到磁性读取地，进一步减小噪声。

公开(公告)号：US06532127B1

公开(公告)日：2003-03-11

申请号：US09714412

申请日：2000-11-16

申请人： Indumini W. Ranmuthu ,  Yuji Isobe

发明人： Indumini W. Ranmuthu ,  Yuji Isobe

IPC分类号： G11B503

CPC分类号： H03F3/45973 ,  G11B5/012 ,  G11B2005/0016 ,  G11B2005/0018 ,  H03F3/45959

摘要： A differential circuit to read differential data from a disk by a voltage bias includes a read circuit to read the differential data from the disk by maintaining the voltage bias and a feedback circuit to sense deviations in the voltage and to adjust the voltage in response to the deviations.

摘要翻译： 通过电压偏压从盘读取差分数据的差分电路包括读取电路，通过维持电压偏置来读取来自盘的差分数据，以及反馈电路来检测电压的偏差并响应于电压而调节电压 偏差

公开(公告)号：US08289832B2

公开(公告)日：2012-10-16

申请号：US12606280

申请日：2009-10-27

申请人： Shengyuan Li ,  Indumini W. Ranmuthu

发明人： Shengyuan Li ,  Indumini W. Ranmuthu

IPC分类号： G11B7/00 ,  G11B7/12

CPC分类号： G11B7/126 ,  H01S5/0428 ,  H01S5/06825 ,  H03F3/45475 ,  H03F2200/168 ,  H03K5/01

摘要： An input signal processing system is described. It comprises a first transconductance device having a first input, second input, and an output, wherein the first input is coupled to receive the input signal; a first resistor coupled to a first input of the first transconductance device, wherein the first resistor converts the input current signal to an input voltage signal; a first voltage-current converter coupled to the output, the second input, the resistor, and a low voltage supply, wherein the first voltage-current converter is operative for converting the input voltage signal to a input current signal; and a low pass filter having an input coupled to the voltage converter for filtering noise from the input current signal.

摘要翻译： 描述输入信号处理系统。 它包括具有第一输入，第二输入和输出的第一跨导装置，其中第一输入被耦合以接收输入信号; 耦合到所述第一跨导装置的第一输入端的第一电阻器，其中所述第一电阻器将所述输入电流信号转换为输入电压信号; 耦合到所述输出端的第一电压 - 电流转换器，所述第二输入端，所述电阻器和低电压电源，其中所述第一电压 - 电流转换器用于将所述输入电压信号转换为输入电流信号; 以及低通滤波器，其具有耦合到电压转换器的输入端，用于滤除来自输入电流信号的噪声。

公开(公告)号：US20100315917A1

公开(公告)日：2010-12-16

申请号：US12622559

申请日：2009-11-20

申请人： Shengyuan Li ,  Indumini W. Ranmuthu ,  Marius V. Dina

发明人： Shengyuan Li ,  Indumini W. Ranmuthu ,  Marius V. Dina

IPC分类号： G11B20/10

CPC分类号： G11B7/126 ,  G11B7/00456

摘要： An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel.

摘要翻译： 描述输入电流通道器件。 该装置包括用于接收参考信号的第一端子; 用于接收第一目标信号的第二终端; 耦合到所述第一终端的通过设备，所述通过设备用于响应于接收到所述参考信号而发送延迟的参考信号; 耦合到所述第一终端和所述第二终端的第一组合逻辑设备，所述第一组合逻辑设备用于响应于接收到所述参考信号和所述第一目标信号而发送第一组合逻辑信号; 耦合用于接收所述延迟的参考信号的选择装置，所述第一组合逻辑信号和第一同步信号，所述选择装置用于选择性地发送第二同步信号，并且其中选择性地发送所述第二同步信号减少所述参考信道和 第一个目标通道。

公开(公告)号：US06490112B1

公开(公告)日：2002-12-03

申请号：US09682320

申请日：2001-08-20

申请人： Indumini W. Ranmuthu ,  Reza Sharifi

发明人： Indumini W. Ranmuthu ,  Reza Sharifi

IPC分类号： G11B503

CPC分类号： G11B5/02 ,  G11B2005/0018

摘要： A circuit (50) and method are presented to provide positive biasing voltages to an MR head (18) in a mass data storage device (10). The circuit (50) includes upper (56) and lower (62) driver transistors to respectively bias respective opposite ends of the MR head (18) with positive voltages. A feedback circuit (58,60,74,84) controls a lower voltage (63) of the positive voltages to be a value as close as possible to a saturation voltage of the lower driver transistor (62), without causing the lower transistor (62) to saturate. Since the MR head (18) is connected between the upper (56) and lower (62) driver transistors, maintaining the lower voltage (63) just above the saturation voltage of the lower driver transistor (62) reduces the common mode voltage across the MR head (18) to a minimum value.

摘要翻译： 呈现电路（50）和方法以向大容量数据存储装置（10）中的MR头（18）提供正偏置电压。 电路（50）包括上（56）和下（62）驱动晶体管，以分别以正电压偏置MR磁头（18）的相应两端。 反馈电路（58,60,74,84）将正电压的较低电压（63）控制为尽可能接近下驱动晶体管（62）的饱和电压的值，而不会使下晶体管（ 62）饱和。 由于MR头（18）连接在上（56）和下（62）驱动晶体管之间，所以保持低于下驱动晶体管（62）的饱和电压的较低电压（63）降低了跨越 MR头（18）达到最小值。

公开(公告)号：US08325583B2

公开(公告)日：2012-12-04

申请号：US12758160

申请日：2010-04-12

申请人： Douglas Warren Dean ,  Shengyuan Li ,  Indumini W. Ranmuthu

发明人： Douglas Warren Dean ,  Shengyuan Li ,  Indumini W. Ranmuthu

IPC分类号： G11B7/00

CPC分类号： G11B7/126 ,  G11B7/00456

摘要： An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode.

摘要翻译： 描述了与激光二极管相关联的光盘驱动器系统。 光盘驱动系统包括用于接收输入信号的电流发生器; 耦合以接收定时信号的电流开关; 电流驱动器，其耦合以从电流开关和电流发生器接收输出信号，所述电流驱动器还包括从由激光二极管读取驱动器和激光二极管写入驱动器组成的组中选择的波形控制的驱动器，其中所述驱动器具有 形状控制用于发送至少一个输出信号，其是从电流发生器接收的至少一个输出信号的缩放版本，其中当前驱动器用于传输驱动该激光二极管的至少一个输出信号。