公开(公告)号：US06490112B1

公开(公告)日：2002-12-03

申请号：US09682320

申请日：2001-08-20

申请人： Indumini W. Ranmuthu ,  Reza Sharifi

发明人： Indumini W. Ranmuthu ,  Reza Sharifi

IPC分类号： G11B503

CPC分类号： G11B5/02 ,  G11B2005/0018

摘要： A circuit (50) and method are presented to provide positive biasing voltages to an MR head (18) in a mass data storage device (10). The circuit (50) includes upper (56) and lower (62) driver transistors to respectively bias respective opposite ends of the MR head (18) with positive voltages. A feedback circuit (58,60,74,84) controls a lower voltage (63) of the positive voltages to be a value as close as possible to a saturation voltage of the lower driver transistor (62), without causing the lower transistor (62) to saturate. Since the MR head (18) is connected between the upper (56) and lower (62) driver transistors, maintaining the lower voltage (63) just above the saturation voltage of the lower driver transistor (62) reduces the common mode voltage across the MR head (18) to a minimum value.

摘要翻译： 呈现电路（50）和方法以向大容量数据存储装置（10）中的MR头（18）提供正偏置电压。 电路（50）包括上（56）和下（62）驱动晶体管，以分别以正电压偏置MR磁头（18）的相应两端。 反馈电路（58,60,74,84）将正电压的较低电压（63）控制为尽可能接近下驱动晶体管（62）的饱和电压的值，而不会使下晶体管（ 62）饱和。 由于MR头（18）连接在上（56）和下（62）驱动晶体管之间，所以保持低于下驱动晶体管（62）的饱和电压的较低电压（63）降低了跨越 MR头（18）达到最小值。

公开(公告)号：US08218259B2

公开(公告)日：2012-07-10

申请号：US12729183

申请日：2010-03-22

申请人： Rajarshi Mukhopadhyay ,  Pankaj Pandey ,  Reza Sharifi

发明人： Rajarshi Mukhopadhyay ,  Pankaj Pandey ,  Reza Sharifi

IPC分类号： G11B5/02 ,  G11B5/09

CPC分类号： H03F3/45282 ,  H03F3/45085 ,  H03F2203/45636

摘要： A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC current signal; a first resistor coupled at one end to a first voltage supply; a first current driver coupled to the input current driver and a first switch control; a second switch coupled a first current driver output, another end of the first resistor, and the output control; a dynamic booster coupled between the first voltage supply and the output control; and wherein the reduced power driver is operative for selectively adding an overshoot current to the output control so that power consumption is reduced, while synchronizing the DC current signal with the overshoot current.

摘要翻译： 描述了一种降低功率的驱动器。 该减小功率驱动器包括：用于发送作为DC电流信号的一部分的电流信号的输入电流驱动器; 第一电阻器，其一端耦合到第一电压源; 耦合到所述输入电流驱动器的第一电流驱动器和第一开关控制; 耦合第一电流驱动器输出的第二开关，第一电阻的另一端和输出控制; 耦合在第一电压源和输出控制之间的动态升压器; 并且其中所述降低功率驱动器用于选择性地向所述输出控制器添加过冲电流，使得在使所述直流电流信号与所述过冲电流同步的同时降低功耗。

公开(公告)号：US20120112868A1

公开(公告)日：2012-05-10

申请号：US13100687

申请日：2011-05-04

申请人： Zhonghua (Ken) Wu ,  Reza Sharifi

发明人： Zhonghua (Ken) Wu ,  Reza Sharifi

IPC分类号： H01F5/04 ,  H05K3/00

CPC分类号： H05K1/165 ,  H01F5/003 ,  H01F41/041 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/0233 ,  H05K1/0298 ,  H05K3/3436 ,  H05K2203/041 ,  Y10T29/49124

摘要： Methods, systems, and apparatuses are provided for three-dimensional coiling via structures. A substrate includes a plurality of insulating layers, a plurality of trace layers interleaved with the insulating layers, and a three-dimensional coiling via. The three-dimensional coiling via includes a plurality of electrically conductive traces and a plurality of electrically conductive vias through the insulating layers. The electrically conductive traces are present in at least two of the traces layers and are coupled together by the electrically conductive vias. The electrically conductive traces are arranged to form at least one partial turn around an axis through the substrate.

摘要翻译： 提供了通过结构进行三维卷取的方法，系统和装置。 衬底包括多个绝缘层，与绝缘层交错的多个迹线层和三维卷绕通孔。 三维卷绕通孔包括多个导电迹线和穿过绝缘层的多个导电通孔。 导电迹线存在于至少两个迹线层中，并通过导电通孔耦合在一起。 导电迹线被布置成围绕穿过基底的轴线形成至少一个部分转弯。

公开(公告)号：US20100237910A1

公开(公告)日：2010-09-23

申请号：US12729183

申请日：2010-03-22

申请人： Rajarshi Mukhopadhyay ,  Pankaj Pandey ,  Reza Sharifi

发明人： Rajarshi Mukhopadhyay ,  Pankaj Pandey ,  Reza Sharifi

IPC分类号： H03B1/00

CPC分类号： H03F3/45282 ,  H03F3/45085 ,  H03F2203/45636

摘要： A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC current signal; a first resistor coupled at one end to a first voltage supply; a first current driver coupled to the input current driver and a first switch control; a second switch coupled a first current driver output, another end of the first resistor, and the output control; a dynamic booster coupled between the first voltage supply and the output control; and wherein the reduced power driver is operative for selectively adding an overshoot current to the output control so that power consumption is reduced, while synchronizing the DC current signal with the overshoot current.

摘要翻译： 描述了一种降低功率的驱动器。 该减小功率驱动器包括：用于发送作为DC电流信号的一部分的电流信号的输入电流驱动器; 第一电阻器，其一端耦合到第一电压源; 耦合到所述输入电流驱动器的第一电流驱动器和第一开关控制; 耦合第一电流驱动器输出的第二开关，第一电阻的另一端和输出控制; 耦合在第一电压源和输出控制之间的动态升压器; 并且其中所述降低功率驱动器用于选择性地向所述输出控制器添加过冲电流，使得在使所述直流电流信号与所述过冲电流同步的同时降低功耗。

公开(公告)号：US20060012902A1

公开(公告)日：2006-01-19

申请号：US10889770

申请日：2004-07-13

申请人： Reza Sharifi

发明人： Reza Sharifi

IPC分类号： G11B5/09 ,  G11B5/02

CPC分类号： G11B5/012 ,  G11B2005/0013 ,  H03F3/45179

摘要： A disk drive data storage system. The system comprises a magnetic disk and a head for writing data to the disk. The system also comprises circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The head is coupled to the first and second nodes such that a data state is written to the disk in response to the first and second voltage. The first and second voltage circuitry comprises a first transistor (421P2) of a first type and coupled to the first node, a first transistor (422N2) of a second type and coupled to the second node, a second transistor (441P2) of the first type and coupled to the second node, and a second transistor (442N2) of the second type and coupled to the second node. The system also comprises circuitry for coupling a first biasing signal (VNDY) to the first transistor of the first type at a first time, and comprising a signal path for the first biasing signal that passes through a base-emitter junction of transistors of both the first and second type. The system also comprises circuitry for coupling a second biasing signal (VPDY) to the first transistor of the second type at the first time, and comprising a signal path for the second biasing signal that passes through a base-emitter junction of transistors of both the first and second type. The system also comprises circuitry for coupling a third biasing signal (VNDX) to the second transistor of the first type at a second time, and comprising a signal path for the third biasing signal that passes through a base-emitter junction of transistors of both the first and second type. Lastly, the system also comprises circuitry for coupling a fourth biasing signal (VPDX) to the second transistor of the second type at the second time, and comprising a signal path for the fourth biasing signal that passes through a base-emitter junction of transistors of both the first and second type.

公开(公告)号：US08421510B2

公开(公告)日：2013-04-16

申请号：US13100819

申请日：2011-05-04

申请人： Diptendu Ghosh ,  Rajarshi Mukhopadhyay ,  Reza Sharifi

发明人： Diptendu Ghosh ,  Rajarshi Mukhopadhyay ,  Reza Sharifi

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/01 ,  G11B20/10009 ,  H03K5/00

摘要： Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others.

摘要翻译： 在硬盘驱动器（HDD）中，例如，前置放大器或前置放大器通常用于使用磁头执行读取和写入操作。 通常，对于写入操作，前置放大器产生电流波形，其使用DC电流来极化磁盘内的磁性元件并过冲组件以补偿头部和前置放大器之间的互连中的频率相关衰减。 用于此应用的常规脉冲整形电路使用高电压来完成此任务。 然而，这里提供了脉冲整形电路，其可以为该应用等使用较低的电压（即约5V）产生类似的波形。

公开(公告)号：US07692889B2

公开(公告)日：2010-04-06

申请号：US12173488

申请日：2008-07-15

申请人： William Martin Torres Escajadillo ,  Pankaj Pandey ,  Reza Sharifi

发明人： William Martin Torres Escajadillo ,  Pankaj Pandey ,  Reza Sharifi

IPC分类号： G11B21/00 ,  G11B21/02 ,  G11B21/12

CPC分类号： H03K5/1565 ,  H03K7/08

摘要： Systems and methods are disclosed that can be used to control an output signal, such as for controlling a heater for a hard disk drive. A system can include a pre-driver configured to provide a pulse-width modulated (PWM) signal to an output system in response to a control signal and a feedback signal, the output system being configured to provide an output signal for driving a load, the pre-driver comprising a modulator that provides the PWM signal in response to the control signal and a filtered feedback signal. A low pass filter is configured to receive a feedback signal with a voltage corresponding to a voltage of the output signal, wherein the low pass filter provides the filtered feedback signal that controls a frequency of the PWM signal to the modulator, the low pass filter having a bulk driven operational transconductance amplifier.

摘要翻译： 公开了可用于控制输出信号的系统和方法，例如用于控制用于硬盘驱动器的加热器。 系统可以包括预驱动器，其配置为响应于控制信号和反馈信号向输出系统提供脉宽调制（PWM）信号，输出系统被配置为提供用于驱动负载的输出信号， 预驱动器包括响应于控制信号和经滤波的反馈信号提供PWM信号的调制器。 低通滤波器被配置为接收具有与输出信号的电压对应的电压的反馈信号，其中低通滤波器提供将经过滤波的反馈信号控制到调制器的PWM信号的频率，低通滤波器具有 大容量驱动的运算跨导放大器。

公开(公告)号：US08723048B2

公开(公告)日：2014-05-13

申请号：US13100687

申请日：2011-05-04

申请人： Zhonghua (Ken) Wu ,  Reza Sharifi

发明人： Zhonghua (Ken) Wu ,  Reza Sharifi

IPC分类号： H05K1/11

CPC分类号： H05K1/165 ,  H01F5/003 ,  H01F41/041 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/0233 ,  H05K1/0298 ,  H05K3/3436 ,  H05K2203/041 ,  Y10T29/49124

摘要： Methods, systems, and apparatuses are provided for three-dimensional coiling via structures. A substrate includes a plurality of insulating layers, a plurality of trace layers interleaved with the insulating layers, and a three-dimensional coiling via. The three-dimensional coiling via includes a plurality of electrically conductive traces and a plurality of electrically conductive vias through the insulating layers. The electrically conductive traces are present in at least two of the traces layers and are coupled together by the electrically conductive vias. The electrically conductive traces are arranged to form at least one partial turn around an axis through the substrate.

摘要翻译： 提供了通过结构进行三维卷取的方法，系统和装置。 衬底包括多个绝缘层，与绝缘层交错的多个迹线层和三维卷绕通孔。 三维卷绕通孔包括多个导电迹线和穿过绝缘层的多个导电通孔。 导电迹线存在于至少两个迹线层中，并通过导电通孔耦合在一起。 导电迹线被布置成围绕穿过基底的轴线形成至少一个部分转弯。

公开(公告)号：US08625214B2

公开(公告)日：2014-01-07

申请号：US13224696

申请日：2011-09-02

申请人： Toru Takeuchi ,  Reza Sharifi

发明人： Toru Takeuchi ,  Reza Sharifi

IPC分类号： G11B27/36 ,  G11B20/10 ,  G11B15/48

CPC分类号： G11B27/36 ,  G11B5/6076

摘要： An apparatus comprises a root mean square (‘RMS’) value generator; an integrator coupled to the RMS value generator; a sample and hold switch coupled to an output of the integrator; a capacitor coupled between the sample and hold switch and a ground; an input of the analog to digital convertor (‘ADC’) coupled to the capacitor; an adder coupled to an output of the ADC; a register, wherein an output of the register is coupled to an input of the adder; and wherein an output of the adder is coupled to an input of the register; and a logic coupled to the register for comparing an output of the register to an RMS threshold value for determining whether a touch-down has occurred.

摘要翻译： 一种装置包括均方根（'RMS'）值发生器; 耦合到RMS值发生器的积分器; 耦合到积分器的输出的采样和保持开关; 耦合在采样保持开关和地之间的电容器; 耦合到电容器的模数转换器（“ADC”）的输入; 耦合到ADC的输出的加法器; 寄存器，其中寄存器的输出耦合到加法器的输入; 并且其中所述加法器的输出耦合到所述寄存器的输入; 以及耦合到所述寄存器的逻辑，用于将所述寄存器的输出与RMS阈值进行比较，以用于确定是否发生了向下触发。

公开(公告)号：US20130058201A1

公开(公告)日：2013-03-07

申请号：US13224696

申请日：2011-09-02

申请人： Toru Takeuchi ,  Reza Sharifi

发明人： Toru Takeuchi ,  Reza Sharifi

IPC分类号： G11B27/36

CPC分类号： G11B27/36 ,  G11B5/6076

摘要： An apparatus comprises a root mean square (‘RMS’) value generator; an integrator coupled to the RMS value generator; a sample and hold switch coupled to an output of the integrator; a capacitor coupled between the sample and hold switch and a ground; an input of the analog to digital convertor (‘ADC’) coupled to the capacitor; an adder coupled to an output of the ADC; a register, wherein an output of the register is coupled to an input of the adder; and wherein an output of the adder is coupled to an input of the register; and a logic coupled to the register for comparing an output of the register to an RMS threshold value for determining whether a touch-down has occurred.

摘要翻译： 一种装置包括均方根（RMS）值发生器; 耦合到RMS值发生器的积分器; 耦合到积分器的输出的采样和保持开关; 耦合在采样保持开关和地之间的电容器; 耦合到电容器的模数转换器（ADC）的输入; 耦合到ADC的输出的加法器; 寄存器，其中所述寄存器的输出耦合到所述加法器的输入; 并且其中所述加法器的输出耦合到所述寄存器的输入; 以及耦合到所述寄存器的逻辑，用于将所述寄存器的输出与RMS阈值进行比较，以用于确定是否发生了向下触发。