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公开(公告)号：US4558447A
公开(公告)日：1985-12-10
申请号：US470033
申请日：1983-02-28
CPC分类号： G06F11/1625
摘要： Self-test techniques for checking driver circuits connected to a bus are described that particularly involve the detection and isolation of failures in off-chip-drivers and connections.
摘要翻译： 描述了用于检查连接到总线的驱动器电路的自检技术，其特别涉及片外驱动器和连接中的故障的检测和隔离。
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公开(公告)号：US3972023A
公开(公告)日：1976-07-27
申请号：US537471
申请日：1974-12-30
申请人： Ronald E. Bodner , Mario N. Cianciosi , Thomas L. Crooks , Israel B. Magrisso , Keith K. Slack , Richard S. Smith
发明人： Ronald E. Bodner , Mario N. Cianciosi , Thomas L. Crooks , Israel B. Magrisso , Keith K. Slack , Richard S. Smith
CPC分类号： G06F13/282 , G06F13/4226
摘要： Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.
摘要翻译： 输入/输出（I / O）设备和中央处理器（CPU）之间的数据传输在指令或基本周期下进行，在I / O设备附件连接到端口的时候窃取控制字节，端口连接到 中央处理器。 数据传输可以是同步还是异步。 涉及数据传输的端口分别向端口数据总线输出设备地址和命令信息，并将命令总线输出到I / O附件。 寻址的I / O设备可以在预定时间间隔内任何时间响应。 如果I / O设备在时间间隔内没有响应，端口产生的爆炸条件会导致I / O附件清除其与端口之间的总线。 在执行I / O指令期间，CPU时钟首先被保持在特定的时间状态，同时相位时钟和端口时钟继续运行，并且端口和I / O附件之间的同步正在进行。 在完成同步序列时，端口产生提前时间信号给CPU以提前CPU时钟。 CPU时钟运行，并且可以根据执行的I / O指令的类型来激活存储时钟，CPU时钟运行直到达到第二特定时间状态，然后保持在该特定时间状态，直到端口再次产生提前 时间信号到CPU。 CPU时钟正在进行的活动取决于I / O指令的类型，但通常会发生数据传输，并将数据输入到本地存储寄存器或主存储器或控制存储器中。 扩展的第二特定时间状态用于端口和I / O附件之间的去同步序列。
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公开(公告)号：US3961312A
公开(公告)日：1976-06-01
申请号：US488349
申请日：1974-07-15
CPC分类号： G06F13/18 , G06F13/282
摘要： Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.
摘要翻译： 计算机系统中的控制电路响应于以突发或专用数据传输模式工作的I / O附件的允许循环窃取信号，并且产生控制信号，从而使得下一个数据存储周期对I / O设备可用 也能够在循环盗取模式下运行。 在下一个存储周期完成后，操作恢复到突发模式，并且在突发模式下操作的I / O附件被授予随后的数据存储周期，直到它将存储周期放弃到能够使用和需要的I / O设备 为了它。
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公开(公告)号：US3961313A
公开(公告)日：1976-06-01
申请号：US529677
申请日：1974-12-04
CPC分类号： G06F9/30054
摘要： The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.
摘要翻译： 在以非重叠模式操作的计算机系统中将分支提取到指令时，取消指令获取周期的第一时间段。 每当分支指令被解码时，存储地址寄存器（SAR）在执行分支指令期间被直接加载，来自存储数据寄存器（SDR）的某些位与来自操作数寄存器的特定位相连，以形成分支到地址在SAR 。 指令计数器以通常的方式增加，但递增的地址不会加载到SAR。 时钟提前到下一个指令获取周期的第二个而不是第一个时间状态。 此后，驻留在操作数寄存器中的地址的分支被递增并加载到指令计数器中。
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