公开(公告)号：US20090127609A1

公开(公告)日：2009-05-21

申请号：US12232020

申请日：2008-09-10

Applicant: Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

Inventor： Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/3247 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/78

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract translation: 提供一种制造凹槽通道晶体管和相关半导体器件的方法。 该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。 电介质隔离物可以保留在栅电极和衬底之间。

公开(公告)号：US09281362B2

公开(公告)日：2016-03-08

申请号：US14286441

申请日：2014-05-23

Applicant: Ja-Young Lee ,  Se-myeong Jang

Inventor： Ja-Young Lee ,  Se-myeong Jang

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11531

Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.

Abstract translation: 根据示例性实施例，半导体器件包括具有单元阵列区域和外围电路区域的衬底。 衬底包括由电池阵列区域中的第一沟槽隔离区域限定的第一有源区，由外围电路区域中的第二沟槽隔离区限定的第二有源区和至少一个深沟槽隔离区。 第一有源区可以对齐以在单元阵列区域中沿第一方向纵向延伸。 所述至少一个深沟槽隔离区域在所述衬底中凹陷到比所述外围电路区域中的所述第二沟槽隔离区域的底表面的其它点的电平低的水平。 所述至少一个深沟槽隔离区域包括在第一方向上与相应的第一有源区域间隔开的至少一个点。

公开(公告)号：US08969936B2

公开(公告)日：2015-03-03

申请号：US13732344

申请日：2012-12-31

Applicant: Wonchul Lee ,  Eun A Kim ,  Ja Young Lee

Inventor： Wonchul Lee ,  Eun A Kim ,  Ja Young Lee

IPC: H01L27/108 ,  H01L27/04 ,  H01L27/02

CPC classification number: H01L27/04 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括：衬底，其包括第一和第二接合区域，埋在衬底中的字线，设置在字线上以跨越字线的位线;设置在衬底和位线之间的电连接 以及设置在位线之间并电连接到第二结区的第二接触。 第二触点的下部的重叠区域可以大于第二触点的上部相对于第二接合区域的重叠区域。

公开(公告)号：US20150091127A1

公开(公告)日：2015-04-02

申请号：US14286441

申请日：2014-05-23

Applicant: Ja-Young LEE ,  Se-myeong JANG

Inventor： Ja-Young LEE ,  Se-myeong JANG

IPC: H01L27/115 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11531

Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.

Abstract translation: 根据示例性实施例，半导体器件包括具有单元阵列区域和外围电路区域的衬底。 衬底包括由电池阵列区域中的第一沟槽隔离区域限定的第一有源区，由外围电路区域中的第二沟槽隔离区限定的第二有源区和至少一个深沟槽隔离区。 第一有源区可以对齐以在单元阵列区域中沿第一方向纵向延伸。 所述至少一个深沟槽隔离区域在所述衬底中凹陷到比所述外围电路区域中的所述第二沟槽隔离区域的底表面的其它点的电平低的水平。 所述至少一个深沟槽隔离区域包括在第一方向上与相应的第一有源区域间隔开的至少一个点。

公开(公告)号：US20080296670A1

公开(公告)日：2008-12-04

申请号：US12128190

申请日：2008-05-28

Applicant: Ja-Young Lee ,  Jin-Woo Lee ,  Sung-Hee Han ,  Tai-Su Park ,  Hyun-Sook Byun

Inventor： Ja-Young Lee ,  Jin-Woo Lee ,  Sung-Hee Han ,  Tai-Su Park ,  Hyun-Sook Byun

IPC: H01L49/00 ,  H01L21/26

CPC classification number: H01L29/66621 ,  H01L21/26586 ,  H01L29/78

Abstract: Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.

Abstract translation: 本发明的一些实施例提供半导体器件，其包括半导体衬底的有源区中的栅极沟槽和栅极沟槽中的栅电极。 在与栅极沟槽的侧壁相邻的有源区域中提供低浓度杂质区域。 在低浓度杂质区域和栅极沟槽的侧壁之间并且沿着栅极沟槽的侧壁设置高浓度杂质区域。 本文还提供了制造半导体器件的相关方法。

公开(公告)号：US07923331B2

公开(公告)日：2011-04-12

申请号：US12232020

申请日：2008-09-10

Applicant: Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

Inventor： Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

IPC: H01L21/336

CPC classification number: H01L21/3247 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/78

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract translation: 提供一种制造凹槽通道晶体管和相关半导体器件的方法。 该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。 电介质隔离物可以保留在栅电极和衬底之间。

公开(公告)号：US20130256828A1

公开(公告)日：2013-10-03

申请号：US13732344

申请日：2012-12-31

Applicant: WONCHUL LEE ,  Eun A. KIM ,  Ja Young LEE

Inventor： WONCHUL LEE ,  Eun A. KIM ,  Ja Young LEE

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括：衬底，其包括第一和第二接合区域，埋在衬底中的字线，设置在字线上以跨越字线的位线;设置在衬底和位线之间的电连接 以及设置在位线之间并电连接到第二结区的第二接触。 第二触点的下部的重叠区域可以大于第二触点的上部相对于第二接合区域的重叠区域。

公开(公告)号：US20120257145A1

公开(公告)日：2012-10-11

申请号：US13441880

申请日：2012-04-08

Applicant: Ja Young LEE ,  Je Hoon SONG ,  Min Seong CHO

Inventor： Ja Young LEE ,  Je Hoon SONG ,  Min Seong CHO

IPC: G02F1/1347 ,  B05D3/10 ,  B32B37/14 ,  B05D5/06

CPC classification number: G02B5/3083 ,  G02B5/3016 ,  G02B5/3033 ,  Y10T156/10

Abstract: Disclosed are a composite retardation plate, a composite polarizing plate including the same and a method for manufacturing the same. More particularly, a composite retardation plate is prepared by corona or plasma treatment of a face of a liquid crystal coating layer formed on a polymeric base film to improve adhesion therebetween and then directly providing a surface treatment coating layer above the coated film, thus being produced by a simple process without using a glass material while requiring neither an additional base material nor adhesive layer. Therefore, the retardation plate prepared as described above is desirably used as a retarder for a thin-film type display. The present invention also provides a composite polarizing plate including the above retardation plate and a method for manufacturing the foregoing.

Abstract translation: 公开了复合延迟板，包括该复合偏振片的复合偏振片及其制造方法。 更具体地，通过电晕或等离子体处理形成在聚合物基膜上的液晶涂层的表面来改善其之间的粘合性，然后在涂膜上直接提供表面处理涂层，从而制备复合延迟板 通过简单的工艺而不使用玻璃材料，同时不需要额外的基材和粘合剂层。 因此，如上所述制备的延迟板优选用作薄膜型显示器的延迟器。 本发明还提供一种包括上述相位差板的复合偏光板及其制造方法。