公开(公告)号：US20080296736A1

公开(公告)日：2008-12-04

申请号：US11757950

申请日：2007-06-04

Applicant: Qian Fu ,  Shenjian Liu ,  Wonchul Lee ,  Bryan Pu

Inventor： Qian Fu ,  Shenjian Liu ,  Wonchul Lee ,  Bryan Pu

IPC: H01B13/00 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L21/32139 ,  H01L21/32136 ,  H01L21/32137

Abstract: A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once.

Abstract translation: 提供了一种用于蚀刻导电层中不同宽高比特征的方法。 该方法包括：在长宽比依赖沉积物上沉积导电层; 将导电层的纵横比依赖蚀刻蚀刻到导电层中; 并重复沉积和蚀刻至少一次。

公开(公告)号：US09059116B2

公开(公告)日：2015-06-16

申请号：US13252813

申请日：2011-10-04

Applicant: Amit Jain ,  Qian Fu ,  Wonchul Lee

Inventor： Amit Jain ,  Qian Fu ,  Wonchul Lee

IPC: B44C1/22 ,  H01L21/311 ,  H01L21/302 ,  H01L21/3213

CPC classification number: H01L21/32136 ,  H01L21/31122 ,  H01L21/32137

Abstract: A method for etching features into an etch layer through a patterned mask in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a main etch plasma. A bias greater than 600 volts is provided. The bias is pulsed at a frequency between 1 Hz and 20 kHz with a duty cycle less than 45%.

Abstract translation: 提供了通过等离子体处理室中的图案化掩模将特征蚀刻到蚀刻层中的方法。 主蚀刻气体流入等离子体处理室。 主蚀刻气体形成为主蚀刻等离子体。 提供大于600伏特的偏压。 该偏压以占空比小于45％的频率在1Hz和20kHz之间的频率脉冲。

公开(公告)号：US20130256828A1

公开(公告)日：2013-10-03

申请号：US13732344

申请日：2012-12-31

Applicant: WONCHUL LEE ,  Eun A. KIM ,  Ja Young LEE

Inventor： WONCHUL LEE ,  Eun A. KIM ,  Ja Young LEE

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括：衬底，其包括第一和第二接合区域，埋在衬底中的字线，设置在字线上以跨越字线的位线;设置在衬底和位线之间的电连接 以及设置在位线之间并电连接到第二结区的第二接触。 第二触点的下部的重叠区域可以大于第二触点的上部相对于第二接合区域的重叠区域。

公开(公告)号：US20110281438A1

公开(公告)日：2011-11-17

申请号：US12744588

申请日：2008-11-18

Applicant: Wonchul Lee ,  Qian Fu ,  Shenjian Liu ,  Bryan Pu

Inventor： Wonchul Lee ,  Qian Fu ,  Shenjian Liu ,  Bryan Pu

IPC: H01L21/3065 ,  C23F1/08

CPC classification number: H01L21/32136

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract translation: 提供了通过具有更宽和更窄特征的掩模蚀刻导电层的方法。 稳态蚀刻气体流过。 提供稳态RF功率以从蚀刻气体形成等离子体。 在稳态蚀刻气流期间提供脉冲偏压，其中脉冲偏压具有1至10,000Hz之间的频率。 使用由蚀刻气体形成的等离子体将更宽和更窄的特征蚀刻到导电层中。

公开(公告)号：US20090258502A1

公开(公告)日：2009-10-15

申请号：US12422108

申请日：2009-04-10

Applicant: In Deog BAE ,  Qian FU ,  Wonchul LEE ,  Shenjian LIU

Inventor： In Deog BAE ,  Qian FU ,  Wonchul LEE ,  Shenjian LIU

IPC: H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/31122

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract translation: 提供了一种相对于多晶硅材料选择性地蚀刻高k电介质层的方法。 通过Ar溅射部分去除高k电介质层，然后使用包含BCl 3的蚀刻气体蚀刻高k电介质层。 高k电介质层和多晶硅材料可以形成在衬底上。 为了部分去除高k电介质层，将含有Ar的溅射气体设置在其中放置基板的蚀刻室中，从溅射气体产生等离子体，然后停止溅射气体。 为了蚀刻高k电介质层，蚀刻气体被提供到蚀刻室中，从蚀刻气体产生等离子体，然后停止蚀刻气体。

公开(公告)号：US20130256769A1

公开(公告)日：2013-10-03

申请号：US13732353

申请日：2012-12-31

Applicant: Jin-Won JEONG ,  WONCHUL LEE

Inventor： Jin-Won JEONG ,  WONCHUL LEE

IPC: H01L27/105

CPC classification number: H01L27/1052 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在字线之间彼此相邻设置但是通过隔离图案彼此间隔开的存储节点焊盘。 因此，可以防止由于掩模未对准而引起桥接问题。 这能够提高半导体器件的可靠性。

公开(公告)号：US08518282B2

公开(公告)日：2013-08-27

申请号：US12744012

申请日：2008-11-13

Applicant: Wonchul Lee ,  Qian Fu ,  Shenjian Liu ,  Bryan Pu

Inventor： Wonchul Lee ,  Qian Fu ,  Shenjian Liu ,  Bryan Pu

IPC: B44C1/22 ,  H01L21/3065

CPC classification number: H01L21/32136 ,  H01L21/32138

Abstract: A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma.

Abstract translation: 提供了一种用于蚀刻含钨层中不同纵横比的特征的方法。 提供了含有钨蚀刻部件和沉积部件的蚀刻气体。 由所提供的蚀刻气体形成等离子体。 用所提供的等离子体蚀刻用宽而窄的特征图案化的含钨层。

公开(公告)号：US07629255B2

公开(公告)日：2009-12-08

申请号：US11757950

申请日：2007-06-04

Applicant: Qian Fu ,  Shenjian Liu ,  Wonchul Lee ,  Bryan Pu

Inventor： Qian Fu ,  Shenjian Liu ,  Wonchul Lee ,  Bryan Pu

IPC: H01L21/44

CPC classification number: H01L21/32139 ,  H01L21/32136 ,  H01L21/32137

Abstract: A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once.

Abstract translation: 提供了一种用于蚀刻导电层中不同宽高比特征的方法。 该方法包括：在长宽比依赖沉积物上沉积导电层; 将导电层的纵横比依赖蚀刻蚀刻到导电层中; 并重复沉积和蚀刻至少一次。

公开(公告)号：US08802571B2

公开(公告)日：2014-08-12

申请号：US13193195

申请日：2011-07-28

Applicant: Wonchul Lee ,  Qian Fu

Inventor： Wonchul Lee ,  Qian Fu

IPC: H01L21/311

CPC classification number: C23C14/08 ,  C23C14/044 ,  C23C14/345 ,  C23C14/5853 ,  C23C14/5873 ,  H01L21/3065 ,  H01L21/3086

Abstract: A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask.

Abstract translation: 提供了通过等离子体处理室中的图案化硬掩模将特征蚀刻到基于硅的蚀刻层中的方法。 提供硅溅射以将硅从硅基蚀刻层溅射到图案化硬掩模的侧壁上，以在图案化的硬掩模上形成侧壁。 通过图案化的硬掩模蚀刻蚀刻层。

公开(公告)号：US08124538B2

公开(公告)日：2012-02-28

申请号：US12422108

申请日：2009-04-10

Applicant: In Deog Bae ,  Qian Fu ,  Wonchul Lee ,  Shenjian Liu

Inventor： In Deog Bae ,  Qian Fu ,  Wonchul Lee ,  Shenjian Liu

IPC: H01L21/302

CPC classification number: H01L21/31122

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract translation: 提供了一种相对于多晶硅材料选择性地蚀刻高k电介质层的方法。 通过Ar溅射部分去除高k电介质层，然后使用包含BCl 3的蚀刻气体蚀刻高k电介质层。 高k电介质层和多晶硅材料可以形成在衬底上。 为了部分去除高k电介质层，将含有Ar的溅射气体设置在其中放置基板的蚀刻室中，从溅射气体产生等离子体，然后停止溅射气体。 为了蚀刻高k电介质层，蚀刻气体被提供到蚀刻室中，从蚀刻气体产生等离子体，然后停止蚀刻气体。