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    SEMICONDUCTOR DEVICES HAVING DUMMY PATTERNS AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING DUMMY PATTERNS AND METHODS OF FABRICATING THE SAME 有权
    具有DUMMY图案的半导体器件及其制造方法

    公开(公告)号：US20160163686A1

    公开(公告)日：2016-06-09

    申请号：US14962237

    申请日：2015-12-08

    Applicant: Jaehan LEE ,  Won-Seok JUNG ,  Kyungjoong JOO

    Inventor： Jaehan LEE ,  Won-Seok JUNG ,  Kyungjoong JOO

    IPC: H01L27/02 ,  H01L27/115

    CPC classification number: H01L27/11565 ,  H01L27/11512 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括具有单元区域和外围区域的衬底，包括堆叠在衬底的单元区域上的栅极的栅极堆叠。 栅极堆叠的至少一个边缘部分可以具有阶梯结构。 半导体器件还可以包括延伸通过栅极堆叠并被存储层包围的沟道和衬底上的至少两个虚设图案。 所述至少两个虚拟图案可以与栅极堆叠间隔开并且可以彼此间隔开。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20140087555A1

    公开(公告)日：2014-03-27

    申请号：US14091680

    申请日：2013-11-27

    Applicant: Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

    Inventor： Yoonmoon PARK ,  Jae-Hwang SIM ,  Se-Young PARK ,  Keonsoo KIM ,  Jaehan LEE ,  Seungwon SEONG

    IPC: H01L21/768

    CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

    Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20110115093A1

    公开(公告)日：2011-05-19

    申请号：US12950347

    申请日：2010-11-19

    Applicant: Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

    Inventor： Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

    IPC: H01L23/528

    CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

    Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿过芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

    Semiconductor device with dummy contacts
    7.
    发明授权
    Semiconductor device with dummy contacts 有权
    具有虚拟触点的半导体器件

    公开(公告)号：US08598710B2

    公开(公告)日：2013-12-03

    申请号：US12950347

    申请日：2010-11-19

    Applicant: Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

    Inventor： Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

    IPC: H01L23/48

    CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

    Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

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