公开(公告)号：US20180314640A1

公开(公告)日：2018-11-01

申请号：US15851775

申请日：2017-12-22

申请人： Jaesop Kong

发明人： Jaesop Kong

IPC分类号： G06F12/0882 ,  G06F3/06 ,  G11C8/10 ,  G11C8/12 ,  G11C7/12

摘要： A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.

公开(公告)号：US09542152B2

公开(公告)日：2017-01-10

申请号：US14086083

申请日：2013-11-21

申请人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

发明人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F5/12

CPC分类号： G06F5/12 ,  G06F2205/062 ,  G06F2205/126

摘要： A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

摘要翻译： 提供了一种片上系统，包括数据生成器; FIFO缓冲器，其存储从数据生成器在与写指针相对应的存储区域传送的数据; 第一个消费者弹出对应于FIFO缓冲器的第一读指针的存储区的数据; 以及第二个消费者，其弹出对应于FIFO缓冲器的第二读指针的存储区的数据。 FIFO缓冲器根据写指针和第一读指针之间的差异，在第二消费者处请求弹出操作，或者覆盖在与第二读指针相对应的存储区上从数据生成器提供的数据。

公开(公告)号：US08194652B2

公开(公告)日：2012-06-05

申请号：US11360884

申请日：2006-02-23

申请人： Jaesop Kong

发明人： Jaesop Kong

IPC分类号： H04L12/50

CPC分类号： G06F13/4295 ,  H04L7/0008

摘要： A method for serially transmitting data from a system including a serializer for converting a parallel data signal into a serial data signal and a parallelizer for converting the serial data signal into the parallel data signal includes storing a value of the parallel data signal in a register in the parallelizer, generating a serial clock signal independent from a clock signal of the parallel data signal using an external clock source, and recovering the parallel data signal by using the value of the parallel data signal stored in the register.

摘要翻译： 一种用于从包括用于将并行数据信号转换为串行数据信号的串行器的系统串行发送数据的方法和用于将串行数据信号转换为并行数据信号的并行器包括将并行数据信号的值存储在寄存器中 并行器，使用外部时钟源产生独立于并行数据信号的时钟信号的串行时钟信号，以及通过使用存储在寄存器中的并行数据信号的值来恢复并行数据信号。

公开(公告)号：US10691608B2

公开(公告)日：2020-06-23

申请号：US15851775

申请日：2017-12-22

申请人： Jaesop Kong

发明人： Jaesop Kong

IPC分类号： G06F12/08 ,  G06F12/0882 ,  G06F3/06 ,  G11C8/10 ,  G11C8/12 ,  G11C7/12 ,  G11C7/10 ,  G06F13/16 ,  G06F12/1045 ,  G06F12/02

摘要： A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.

公开(公告)号：US20140149694A1

公开(公告)日：2014-05-29

申请号：US14086083

申请日：2013-11-21

申请人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

发明人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

IPC分类号： G06F12/02

CPC分类号： G06F5/12 ,  G06F2205/062 ,  G06F2205/126

摘要： A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

摘要翻译： 提供了一种片上系统，包括数据生成器; FIFO缓冲器，其存储从数据生成器在与写指针相对应的存储区域传送的数据; 第一个消费者弹出对应于FIFO缓冲器的第一读指针的存储区的数据; 以及第二个消费者，其弹出对应于FIFO缓冲器的第二读指针的存储区的数据。 FIFO缓冲器根据写指针和第一读指针之间的差异，在第二消费者处请求弹出操作，或者覆盖在与第二读指针相对应的存储区上从数据生成器提供的数据。

公开(公告)号：US20060193347A1

公开(公告)日：2006-08-31

申请号：US11360884

申请日：2006-02-23

申请人： Jaesop Kong

发明人： Jaesop Kong

IPC分类号： H04J3/06

CPC分类号： G06F13/4295 ,  H04L7/0008

摘要： A method for serially transmitting data from a system including a serializer for converting a parallel data signal into a serial data signal and a parallelizer for converting the serial data signal into the parallel data signal includes storing a value of the parallel data signal in a register in the parallelizer, generating a serial clock signal independent from a clock signal of the parallel data signal using an external clock source, and recovering the parallel data signal by using the value of the parallel data signal stored in the register.

摘要翻译： 一种用于从包括用于将并行数据信号转换为串行数据信号的串行器的系统串行发送数据的方法和用于将串行数据信号转换为并行数据信号的并行器包括将并行数据信号的值存储在寄存器中 并行器，使用外部时钟源产生独立于并行数据信号的时钟信号的串行时钟信号，以及通过使用存储在寄存器中的并行数据信号的值来恢复并行数据信号。