公开(公告)号：US09542152B2

公开(公告)日：2017-01-10

申请号：US14086083

申请日：2013-11-21

申请人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

发明人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F5/12

CPC分类号： G06F5/12 ,  G06F2205/062 ,  G06F2205/126

摘要： A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

摘要翻译： 提供了一种片上系统，包括数据生成器; FIFO缓冲器，其存储从数据生成器在与写指针相对应的存储区域传送的数据; 第一个消费者弹出对应于FIFO缓冲器的第一读指针的存储区的数据; 以及第二个消费者，其弹出对应于FIFO缓冲器的第二读指针的存储区的数据。 FIFO缓冲器根据写指针和第一读指针之间的差异，在第二消费者处请求弹出操作，或者覆盖在与第二读指针相对应的存储区上从数据生成器提供的数据。

公开(公告)号：US20140149694A1

公开(公告)日：2014-05-29

申请号：US14086083

申请日：2013-11-21

申请人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

发明人： Donghan Lee ,  Jaesop Kong ,  Keemoon Chun

IPC分类号： G06F12/02

CPC分类号： G06F5/12 ,  G06F2205/062 ,  G06F2205/126

摘要： A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

摘要翻译： 提供了一种片上系统，包括数据生成器; FIFO缓冲器，其存储从数据生成器在与写指针相对应的存储区域传送的数据; 第一个消费者弹出对应于FIFO缓冲器的第一读指针的存储区的数据; 以及第二个消费者，其弹出对应于FIFO缓冲器的第二读指针的存储区的数据。 FIFO缓冲器根据写指针和第一读指针之间的差异，在第二消费者处请求弹出操作，或者覆盖在与第二读指针相对应的存储区上从数据生成器提供的数据。

公开(公告)号：US08278180B2

公开(公告)日：2012-10-02

申请号：US12871273

申请日：2010-08-30

申请人： Changhun Lee ,  Keemoon Chun

发明人： Changhun Lee ,  Keemoon Chun

IPC分类号： H01L21/331 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76823 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least −20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region.

摘要翻译： 形成具有接触结构的半导体器件的方法包括在半导体衬底上形成绝缘层，并且将杂质离子选择性地注入到绝缘层的预定区域中，以在绝缘层的预定区域中产生晶格缺陷。 对具有晶格缺陷的绝缘层进行热处理，例如以至少-20℃/分钟的温度变化率淬火绝缘层的热处理，以加速预定区域中的晶格缺陷的产生，使得 导电区域由所产生的晶格缺陷产生，以在预定区域中提供电流路径。

公开(公告)号：US09401385B2

公开(公告)日：2016-07-26

申请号：US14639183

申请日：2015-03-05

申请人： Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

发明人： Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

IPC分类号： H01L29/66 ,  H01L29/82 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

摘要： The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

摘要翻译： 本发明构思提供了包括可变电阻存储器元件的半导体存储器件。 半导体存储器件可以包括设置在距离半导体衬底的第一高度处的第一位线，与半导体衬底相比设置在与第一高度不同的第二高度的第二位线，连接到第一可变电阻存储器元件 到第一位线，以及连接到第二位线的第二可变电阻存储元件。 第一和第二可变电阻存储器元件可以设置在与半导体衬底基本相同的高度处。

公开(公告)号：US20150357376A1

公开(公告)日：2015-12-10

申请号：US14639183

申请日：2015-03-05

申请人： Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

发明人： Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

IPC分类号： H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

摘要： The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

摘要翻译： 本发明构思提供了包括可变电阻存储器元件的半导体存储器件。 半导体存储器件可以包括设置在距离半导体衬底的第一高度处的第一位线，与半导体衬底相比设置在与第一高度不同的第二高度的第二位线，连接到第一可变电阻存储器元件 到第一位线，以及连接到第二位线的第二可变电阻存储元件。 第一和第二可变电阻存储器元件可以设置在与半导体衬底基本相同的高度处。

公开(公告)号：US20110151658A1

公开(公告)日：2011-06-23

申请号：US12871273

申请日：2010-08-30

申请人： Changhun Lee ,  Keemoon Chun

发明人： Changhun Lee ,  Keemoon Chun

IPC分类号： H01L21/768

CPC分类号： H01L21/76823 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least −20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region.

摘要翻译： 形成具有接触结构的半导体器件的方法包括在半导体衬底上形成绝缘层，并且将杂质离子选择性地注入到绝缘层的预定区域中，以在绝缘层的预定区域中产生晶格缺陷。 对具有晶格缺陷的绝缘层进行热处理，例如以至少-20℃/分钟的温度变化率淬火绝缘层的热处理，以加速预定区域中的晶格缺陷的产生，使得 导电区域由所产生的晶格缺陷产生，以在预定区域中提供电流路径。