公开(公告)号：US08450784B2

公开(公告)日：2013-05-28

申请号：US13049746

申请日：2011-03-16

申请人： Jaeyoun Kim ,  Jaihyuk Song ,  Manki Lee ,  Bongtae Park

发明人： Jaeyoun Kim ,  Jaihyuk Song ,  Manki Lee ,  Bongtae Park

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/70

CPC分类号： H01L27/11548 ,  H01L27/11519 ,  H01L27/11529

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes lateral and upper hydrogen blocking patterns disposed to prevent hydrogen from diffusing into the cell array region. Accordingly, hydrogen is effectively prevented from being trapped in a tunnel dielectric, thereby improving the reliability of the semiconductor device. In the method, when a cell array contact plug is formed, a lateral hydrogen blocking pattern and an upper hydrogen blocking pattern are formed at the same time. Thus, an additional process for forming a hydrogen blocking pattern is unnecessary, thereby simplifying a process.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括设置为防止氢扩散到电池阵列区域中的侧向和上部氢气阻挡图案。 因此，有效地防止了氢被捕获在隧道电介质中，从而提高了半导体器件的可靠性。 在该方法中，当形成电池阵列接触塞时，同时形成横向氢阻挡图案和上部氢阻挡图案。 因此，不需要用于形成氢阻挡图案的附加工艺，从而简化了工艺。

公开(公告)号：US20150063037A1

公开(公告)日：2015-03-05

申请号：US14471231

申请日：2014-08-28

申请人： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

发明人： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.

摘要翻译： 提供了非易失性存储器件和相关方法。 非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底 和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管 地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

公开(公告)号：US09165660B2

公开(公告)日：2015-10-20

申请号：US14471231

申请日：2014-08-28

申请人： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

发明人： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.

摘要翻译： 提供了非易失性存储器件和相关方法。 非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底 和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管 地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

公开(公告)号：US20110248317A1

公开(公告)日：2011-10-13

申请号：US13049746

申请日：2011-03-16

申请人： Jaeyoun Kim ,  Jaihyuk Song ,  Manki Lee ,  Bongtae Park

发明人： Jaeyoun Kim ,  Jaihyuk Song ,  Manki Lee ,  Bongtae Park

IPC分类号： H01L27/10

CPC分类号： H01L27/11548 ,  H01L27/11519 ,  H01L27/11529

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes lateral and upper hydrogen blocking patterns disposed to prevent hydrogen from diffusing into the cell array region. Accordingly, hydrogen is effectively prevented from being trapped in a tunnel dielectric, thereby improving the reliability of the semiconductor device. In the method, when a cell array contact plug is formed, a lateral hydrogen blocking pattern and an upper hydrogen blocking pattern are formed at the same time. Thus, an additional process for forming a hydrogen blocking pattern is unnecessary, thereby simplifying a process.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括设置为防止氢扩散到电池阵列区域中的侧向和上部氢气阻挡图案。 因此，有效地防止了氢被捕获在隧道电介质中，从而提高了半导体器件的可靠性。 在该方法中，当形成电池阵列接触塞时，同时形成横向氢阻挡图案和上部氢阻挡图案。 因此，不需要用于形成氢阻挡图案的附加工艺，从而简化了工艺。