公开(公告)号：US09165660B2

公开(公告)日：2015-10-20

申请号：US14471231

申请日：2014-08-28

Applicant: Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

Inventor： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.

Abstract translation: 提供了非易失性存储器件和相关方法。 非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底 和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管 地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

公开(公告)号：US20150063037A1

公开(公告)日：2015-03-05

申请号：US14471231

申请日：2014-08-28

Applicant: Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

Inventor： Dong-Jun Lee ,  Sungsu Moon ,  Jaihyuk Song ,  Changsub Lee

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.

Abstract translation: 提供了非易失性存储器件和相关方法。 非易失性存储器件包括具有多个单元串的存储单元阵列，每个单元串包括：沿垂直于衬底的方向堆叠的多个存储单元，多个存储单元之间的接地选择晶体管和衬底 和多个存储单元之间的串选择晶体管和位线; 通过字线将多个单元串中的多个存储单元耦合到地址解码器，通过串选择线连接到多个单元串中的串选择晶体管，以及通过一个单元串的多个单元串中的地选择晶体管 地面选线; 读/写电路，通过位线耦合到多个单元串中的串选择晶体管; 以及控制逻辑，被配置为调整施加到所述衬底的衬底电压，使得所述接地选择晶体管的阈值电压在所述多个单元串中的所述多个存储器单元中的至少一个的读操作期间高于预定电平。

公开(公告)号：US20160118126A1

公开(公告)日：2016-04-28

申请号：US14854097

申请日：2015-09-15

Applicant: Sungsu Moon ,  Changsub LEE ,  Raeyoung LEE ,  Soyeong GWAK

Inventor： Sungsu Moon ,  Changsub LEE ,  Raeyoung LEE ,  Soyeong GWAK

IPC: G11C16/12 ,  G11C16/34 ,  G06F12/02

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A program method of a nonvolatile memory device is provided which includes programming memory cells to a target state using a verification voltage and an incremental step pulse, selecting memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells programmed to the target state, and applying a supplementary program voltage to the selected memory cells. The supplementary verification voltage is equal to or higher than the verification voltage, and the supplementary program voltage is equal to or lower than a program voltage provided in a program loop where a programming of the memory cells to the target state is completed.

Abstract translation: 提供了一种非易失性存储器件的编程方法，其包括使用验证电压和增量步进脉冲将存储器单元编程为目标状态，从存储单元中选择各自具有低于辅助验证电压的阈值电压的存储单元 被编程到目标状态，并将补充编程电压施加到所选存储单元。 辅助验证电压等于或高于验证电压，并且补充编程电压等于或低于在编程到目标状态的存储器单元的程序循环中提供的编程电压。