公开(公告)号：US07294544B1

公开(公告)日：2007-11-13

申请号：US09249254

申请日：1999-02-12

申请人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

发明人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/8221 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is deposited overlying the insulating layer and the metal plugs. A capacitor dielectric layer is deposited overlying the first metal layer wherein capacitor dielectric layer is deposited as a dual layer, each layer deposited within a separate chamber whereby pinholes are eliminated. A second metal layer and a barrier metal layer are deposited overlying the capacitor dielectric layer. The second metal layer and the barrier metal layer are patterned to form a top plate electrode. Thereafter, the capacitor dielectric layer and the first metal layer are patterned to form a bottom plate electrode completing fabrication of a metal-insulator-metal capacitor.

摘要翻译： 实现了一种制造改进的金属 - 绝缘体 - 金属电容器的方法。 在半导体衬底上覆盖导电线的绝缘层。 通过绝缘层到导线的开口填充有金属插头。 沉积在绝缘层和金属插头上的第一金属层。 电容器电介质层沉积在第一金属层上，其中电容器电介质层被沉积为双层，每层沉积在单独的室内，由此消除针孔。 沉积在电容器介电层上的第二金属层和阻挡金属层。 将第二金属层和阻挡金属层图案化以形成顶板电极。 此后，对电容器电介质层和第一金属层进行图案化以形成完成金属 - 绝缘体 - 金属电容器的制造的底板电极。

公开(公告)号：US06667217B1

公开(公告)日：2003-12-23

申请号：US09795115

申请日：2001-03-01

申请人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

发明人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F41/042 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

摘要翻译： 已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。 集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。 在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构， 以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。 与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。