公开(公告)号：US08694845B2

公开(公告)日：2014-04-08

申请号：US12766886

申请日：2010-04-25

申请人： Ssu-Pin Ma

发明人： Ssu-Pin Ma

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/2843 ,  G01R31/31932 ,  H01L2224/05554

摘要： A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion to be tested, a comparator and a comparison result recorder. The circuit portion to be tested receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. Then, the comparator outputs a comparison result according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The comparison result recorder may record comparison results within a period of test time. The test instrument can obtain a record of the comparison results from the comparison result recorder.

摘要翻译： 用于测试电子电路的系统被配置为接收测试信号和理想响应信号并输出​​测试结果信号。 用于测试电子电路的系统包括要测试的电路部分，比较器和比较结果记录器。 要测试的电路部分接收来自测试仪器的测试信号，并输出系统响应信号。 比较器从要测试的电路部分接收系统响应信号，并从测试仪器接收理想的响应信号。 然后，比较器根据系统响应信号和理想响应信号输出比较结果。 比较结果记录器接收并记录比较结果。 比较结果记录仪可以在测试时间内记录比较结果。 测试仪器可以从比较结果记录仪中获得比较结果的记录。

公开(公告)号：US20130156140A1

公开(公告)日：2013-06-20

申请号：US13326248

申请日：2011-12-14

申请人： Sujai Chari ,  Ssu-Pin Ma

发明人： Sujai Chari ,  Ssu-Pin Ma

IPC分类号： H04L27/08 ,  H04B7/00 ,  H04B1/06

CPC分类号： H03G3/3068 ,  H04B2001/1054

摘要： Apparatuses, methods and systems of selecting a gain setting of a receiver chain are disclosed. One method includes bypassing a filter portion of the receiver chain and sampling a bypass receive signal while the filter portion of the receiver chain is bypassed. If the sampled bypass receive signal is determined to be saturated greater than a threshold, then selecting a gain setting of the receive chain as a function of the saturation. Further, the filter portion of the receive chain is included while sampling a receive signal with the selected gain setting.

摘要翻译： 公开了选择接收机链的增益设置的设备，方法和系统。 一种方法包括绕过接收器链的滤波器部分并对旁路接收信号进行采样，同时接收器链的滤波器部分被旁路。 如果采样旁路接收信号被确定为饱和大于阈值，则选择接收链的增益设置作为饱和度的函数。 此外，包括接收链的滤波器部分，同时采用所选择的增益设置对接收信号进行采样。

公开(公告)号：US20110078649A1

公开(公告)日：2011-03-31

申请号：US12571212

申请日：2009-09-30

申请人： Ssu-Pin Ma

发明人： Ssu-Pin Ma

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068

摘要： A wafer layout assisting method is used to assist a circuit designer to estimate the layout related parameter during a circuit designing process. The wafer layout assisting method includes the following steps. A circuit information file is read. A graphic user interface (GUI) is generated according to the circuit information file. A coarse layout arrangement input by a user is received. It is determined whether the coarse layout arrangement is finished or not. A layout related parameter is generated according to device types, device parameters, and the coarse layout arrangement, if the coarse layout arrangement is finished. The circuit designer may increase an accuracy of a circuit simulation result by appropriately utilizing the layout related parameters. Through the wafer layout assisting method, the layout related parameter after the layout is performed may be pre-estimated, thus reducing a difference between the circuit simulation results before and after the layout is performed.

摘要翻译： 使用晶片布局辅助方法来帮助电路设计者在电路设计过程期间估计布局相关参数。 晶片布局辅助方法包括以下步骤。 读取电路信息文件。 根据电路信息文件生成图形用户界面（GUI）。 接收用户输入的粗略布局布置。 确定粗布局布置是否完成。 布局相关参数根据设备类型，设备参数和粗略布局布局生成，如果粗布局布局完成。 电路设计者可以通过适当地利用布局相关参数来提高电路仿真结果的精度。 通过晶片布局辅助方法，可以预先布置布局后的布局相关参数，从而减少布局之前和之后的电路仿真结果之间的差异。

公开(公告)号：US20110050273A1

公开(公告)日：2011-03-03

申请号：US12547268

申请日：2009-08-25

申请人： Ssu Pin Ma

发明人： Ssu Pin Ma

IPC分类号： G01R1/06 ,  G01R31/26 ,  G01R31/02

CPC分类号： G01R31/318511 ,  H01L22/32 ,  H01L2224/05554

摘要： A fast testable wafer includes a die group, testing points located on dies, a scribe line located between the dies, and a plurality of testing pads disposed in the scribe line area. The testing points comprise bonding pads or electrodes of internal circuits within the dies. The testing pads and bonding pads may be electrically connected and arranged suitably such that testing probes may be electrically connected to the testing pads and bonding pads easily so as to test the plurality of dies at about the same time. Through suitable circuits on the wafer, different circuit routes may be selected to connect the testing pads and different testing points on the dies so as to test a plurality of dies without moving the testing probes and thereby accelerating the test.

摘要翻译： 快速可测试的晶片包括模具组，位于模具上的测试点，位于模具之间的划线，以及设置在划线区域中的多个测试焊盘。 测试点包括模具内的内部电路的焊盘或电极。 测试焊盘和接合焊盘可以电连接和适当布置，使得测试探针可以容易地电连接到测试焊盘和焊盘，以便在大约同时间测试多个裸片。 通过晶片上的适当电路，可以选择不同的电路路线来连接测试焊盘和模具上的不同测试点，以便在不移动测试探针的情况下测试多个模具，从而加速测试。

公开(公告)号：US07623886B2

公开(公告)日：2009-11-24

申请号：US11300089

申请日：2005-12-14

申请人： Ssu-Pin Ma ,  Isaac Sever

发明人： Ssu-Pin Ma ,  Isaac Sever

IPC分类号： H04B7/00

CPC分类号： H04W52/225 ,  H04B17/13 ,  H04W52/52

摘要： A method and apparatus of calibrating a transmitter are disclosed. The method includes attenuating transmitter output signals as controlled by an output control signal, ensuring that an average power of the transmitter output signals is below a threshold level, and performing calibration of the transmitter at periods of time in which the output control signal is attenuating the transmitter output signals a lesser amount. The lesser amount can be less than an average of a minimum amount of attenuation and a maximum amount of attenuation. The apparatus includes a transmitter that includes a frequency up-converting LO mixer for frequency up-converting base band signals, generating transmitter output signals, a transmitter antenna for transmitting the transmitter output signals, and control circuitry for controlling attenuating the transmitter output signals during a calibration of the transmitter.

摘要翻译： 公开了校准发射机的方法和装置。 该方法包括衰减由输出控制信号控制的发射机输出信号，确保发射机输出信号的平均功率低于阈值电平，并且在输出控制信号正在衰减的时间段执行发射机的校准 发射机输出信号的数量较少。 较小的量可以小于最小衰减量和最大衰减量的平均值。 该装置包括发射机，其包括用于频率上变频基带信号的上变频LO混频器，产生发射机输出信号，用于发送发射机输出信号的发射机天线，以及控制电路，用于控制在 变送器的校准。

公开(公告)号：US20070135058A1

公开(公告)日：2007-06-14

申请号：US11300089

申请日：2005-12-14

申请人： Ssu-Pin Ma ,  Isaac Sever

发明人： Ssu-Pin Ma ,  Isaac Sever

IPC分类号： H04B7/00

CPC分类号： H04W52/225 ,  H04B17/13 ,  H04W52/52

摘要： A method and apparatus of calibrating a transmitter are disclosed. The method includes attenuating transmitter output signals as controlled by an output control signal, ensuring that an average power of the transmitter output signals is below a threshold level, and performing calibration of the transmitter at periods of time in which the output control signal is attenuating the transmitter output signals a lesser amount. The lesser amount can be less than an average of a minimum amount of attenuation and a maximum amount of attenuation. The apparatus includes a transmitter that includes a frequency up-converting LO mixer for frequency up-converting base band signals, generating transmitter output signals, a transmitter antenna for transmitting the transmitter output signals, and control circuitry for controlling attenuating the transmitter output signals during a calibration of the transmitter.

摘要翻译： 公开了校准发射机的方法和装置。 该方法包括衰减由输出控制信号控制的发射机输出信号，确保发射机输出信号的平均功率低于阈值电平，并且在输出控制信号正在衰减的时间段执行发射机的校准 发射机输出信号的数量较少。 较小的量可以小于最小衰减量和最大衰减量的平均值。 该装置包括发射机，其包括用于频率上变频基带信号的上变频LO混频器，产生发射机输出信号，用于发送发射机输出信号的发射机天线，以及控制电路，用于控制在 变送器的校准。

公开(公告)号：US20070093224A1

公开(公告)日：2007-04-26

申请号：US11258701

申请日：2005-10-26

申请人： Steve Lo ,  Isaac Sever ,  Thai Nguyen ,  Ssu-Pin Ma

发明人： Steve Lo ,  Isaac Sever ,  Thai Nguyen ,  Ssu-Pin Ma

IPC分类号： H04B1/06

CPC分类号： H04B1/1027

摘要： A method and apparatus of calibrating filtering of receive and transmit signals is disclosed. The method of calibrating filtering of a received signal includes injecting an LO signal. The injected LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filtering. A desired filter tuning is determined based upon the samples and a frequency of the LO signal. The method of calibrating filtering of a transmit signal includes injecting an LO signal to a transmitter. The LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filter. A desired filter tuning is determined based upon the samples and a frequency of the LO signal.

摘要翻译： 公开了一种校准接收和发送信号的滤波的方法和装置。 对接收信号进行校准滤波的方法包括：注入LO信号。 注入的LO信号被可调滤波器滤波。 滤波后的信号用等效的LO信号进行降频转换。 在对滤波进行调谐的同时对降频转换信号进行采样。 基于样本和LO信号的频率来确定期望的滤波器调谐。 校准发射信号的滤波的方法包括将LO信号注射到发射机。 LO信号由可调谐滤波器滤波。 滤波后的信号用等效的LO信号进行降频转换。 在对滤波器进行调谐的同时采样降频转换信号。 基于样本和LO信号的频率来确定期望的滤波器调谐。

公开(公告)号：US07038294B2

公开(公告)日：2006-05-02

申请号：US09821521

申请日：2001-03-29

申请人： Ssu-Pin Ma ,  Yen-Shih Ho

发明人： Ssu-Pin Ma ,  Yen-Shih Ho

IPC分类号： H01L29/00

CPC分类号： H01L24/05 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S257/909 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

公开(公告)号：US20050029566A1

公开(公告)日：2005-02-10

申请号：US10935376

申请日：2004-09-07

申请人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

发明人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/08 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

摘要翻译： 描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。 该方法提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。 该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。 在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。 使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。 沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。 厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

公开(公告)号：US06812088B1

公开(公告)日：2004-11-02

申请号：US10167856

申请日：2002-06-11

申请人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

发明人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

摘要翻译： 该MIM结构提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。 形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺同时形成焊盘触点和铜互连水平。 在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。 金属保护缓冲器保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。 沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。 厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。