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    Selective cooling of an integrated circuit for minimizing power loss
    2.
    发明授权
    Selective cooling of an integrated circuit for minimizing power loss 有权
    集成电路的选择性冷却，以最大限度地减少功率损耗

    公开(公告)号：US06825687B2

    公开(公告)日：2004-11-30

    申请号：US10230466

    申请日：2002-08-29

    Applicant: Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

    Inventor： Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

    IPC: H03K1716

    CPC classification number: H03K19/0016 ,  H01L27/0251

    Abstract: An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

    Abstract translation: 一种用于降低在集成电路中使用的晶体管的泄漏电流的装置和方法，其选择性地将集成电路中的处理器电路切换到待机状态。 包括冷却装置并且选择性地位于集成电路的紧邻用于在主动状态和待机状态之间切换处理器电路的晶体管的区域中。 冷却装置冷却晶体管，以改善其泄漏和有功电流状态，从而提高晶体管的效率并减少其漏电流。

    Double gate transistor for low power circuits
    3.
    发明授权
    Double gate transistor for low power circuits 有权
    用于低功率电路的双栅极晶体管

    公开(公告)号：US07053449B2

    公开(公告)日：2006-05-30

    申请号：US10254346

    申请日：2002-09-24

    Applicant: Jaume A. Segura ,  Ali Keshavarzi ,  Vivek K. De

    Inventor： Jaume A. Segura ,  Ali Keshavarzi ,  Vivek K. De

    IPC: H01L29/76

    CPC classification number: H01L29/7831

    Abstract: A double gate MOSFET having a control gate and a signal gate. The effective threshold voltage seen by the signal gate may be modified by charging the control gate. The effective threshold voltage may be increased in magnitude to reduce sub-threshold leakage current when the double gate MOSFET is inactive. When inactive, the control gate is maintained at a negative voltage for a double gate nMOSFET, and is maintained at a positive voltage for a double gate pMOSFET. When active, the control gate is charged to a voltage close to the threshold voltage, and then floated, so that a signal voltage applied to the signal gate may turn the double gate MOSFET ON during a signal voltage transition via the coupling capacitance between the signal and control gates.

    Abstract translation: 具有控制栅极和信号栅极的双栅极MOSFET。 可以通过对控制栅极充电来修改由信号门看到的有效阈值电压。 当双栅极MOSFET不活动时，有效阈值电压可以增加幅度以减小次阈值漏电流。 当不活动时，对于双栅极nMOSFET，控制栅极保持在负电压，并且对于双栅极pMOSFET保持在正电压。 当激活时，控制栅极被充电到接近阈值电压的电压，然后漂浮，使得施加到信号栅极的信号电压可以在信号电压转换期间通过信号之间的耦合电容将双栅极MOSFET导通 和控制门。

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