公开(公告)号：US08903013B2

公开(公告)日：2014-12-02

申请号：US13131151

申请日：2009-11-24

申请人： Jean-Luc Danger ,  Sami Mekki ,  Benoît Miscopein

发明人： Jean-Luc Danger ,  Sami Mekki ,  Benoît Miscopein

IPC分类号： H04L27/00 ,  H04B1/7163 ,  H04B1/719 ,  H04B1/69

CPC分类号： H04B1/71637 ,  H04B1/71635 ,  H04B1/719 ,  H04B2001/6908

摘要： A method and apparatus are provided for sending pulses from a sender device to a receiver device in a transmission channel. The pulses represent information symbols, with each of these pulses being associated with a time slot in a symbol time. The method includes a training step that is carried out before sending payload information and that includes sending a training sequence made up of two parts. A first part of the training sequence includes at least one pulse of energy that is greater than the energy of a pulse carrying payload information. There are a large number of time slots between the sending of the pulse and the sending of the next pulse. A second part of the training sequence includes a set of pulses known in advance and similar to the pulses used for carrying payload information, the energy of each of these pulses being equivalent to the energy of a pulse carrying payload information.

摘要翻译： 提供了一种方法和装置，用于在传输信道中从发送器设备向接收器设备发送脉冲。 脉冲表示信息符号，其中每个脉冲与符号时间中的时隙相关联。 该方法包括在发送有效载荷信息之前执行的训练步骤，并且包括发送由两部分组成的训练序列。 训练序列的第一部分包括至少一个能量脉冲，该能量脉冲大于载有有效载荷信息的脉冲的能量。 在发送脉冲和发送下一个脉冲之间有大量的时隙。 训练序列的第二部分包括预先已知的并且类似于用于承载有效载荷信息的脉冲的一组脉冲，这些脉冲中的每一个的能量等同于承载有效载荷信息的脉冲的能量。

公开(公告)号：US08867739B2

公开(公告)日：2014-10-21

申请号：US13522680

申请日：2011-01-10

申请人： Jean-Luc Danger

发明人： Jean-Luc Danger

IPC分类号： G06F21/00 ,  G06F21/31 ,  G06F21/73 ,  H04L9/08 ,  G01R31/317

CPC分类号： H04L9/0861 ,  G01R31/31719 ,  G06F21/31 ,  G06F21/73 ,  G06F2221/2129 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/12 ,  H04L2209/26

摘要： A silicon integrated circuit includes a physically non-copyable function LPUF that generates a signature specific to the circuit. The function includes a ring oscillator composed of a loop traversed by a signal. The loop is formed of N topologically identical chains of lags connected in series and an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also includes a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after updating the control words, and the control module can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided.

摘要翻译： 硅集成电路包括产生电路特有的签名的物理上不可复制的功能LPUF。 该功能包括由信号穿过的环路组成的环形振荡器。 该环路由N个拓扑相同的串联链路和反向门组成，一系列延迟链由M个延迟元件串联组成。 该功能还包括产生N个控制字的控制模块，用于配置由延迟链引入的延迟对穿过它们的信号的值。 测量模块在更新控制字之后测量最后链延迟链输出端的信号频率，并且控制模块可以从频率测量中推断构成电路签名的位。 还提供了用于测试这种电路的方法和系统。

公开(公告)号：US08615079B2

公开(公告)日：2013-12-24

申请号：US13145177

申请日：2010-01-18

申请人： Jean-Luc Danger ,  Sylvain Guilley

发明人： Jean-Luc Danger ,  Sylvain Guilley

IPC分类号： G06F21/00

CPC分类号： H04L9/003 ,  H04L9/0625 ,  H04L2209/046 ,  H04L2209/12

摘要： A cryptography circuit protected against observation attacks comprises at least one register R providing a variable x masked by the mask m, the masked variable being encrypted by a first substitution box S -in a cyclic manner. The circuit also comprises a mask register M delivering at each cycle a mask mt, the transformation of m, the mask m being extracted from mt before being encrypted by a second substitution box S′, the new mask m′ obtained on output from this box S′ is transformed into a mask m′t before being stored in the mask register M. The transformation consists of a bijection or a composition law making it possible to reduce or indeed to cancel any high-order attack in accordance with a model of activity of the registers R and M. Cryptography circuits are protected against high-order observation attacks on installations based on masking.

摘要翻译： 防止观察攻击的密码学电路包括至少一个寄存器R，其提供由掩模m屏蔽的变量x，掩蔽变量由循环方式由第一替换框S加密。 电路还包括一个屏蔽寄存器M，每个周期都传送一个掩码mt，m的变换，m个被提取的掩码m在被第二个替代框S'加密之前，从这个框输出得到的新的掩码m' S'在被存储在掩模寄存器M中之前被转换成掩模。该转换由双射或组合法组成，使得可以根据活动模型减少或确实取消任何高阶攻击 的寄存器R和M.加密电路被保护免受基于掩蔽的安装的高阶观察攻击。

公开(公告)号：US20130202107A1

公开(公告)日：2013-08-08

申请号：US13522680

申请日：2011-01-10

申请人： Jean-Luc Danger

发明人： Jean-Luc Danger

IPC分类号： H04L9/08

CPC分类号： H04L9/0861 ,  G01R31/31719 ,  G06F21/31 ,  G06F21/73 ,  G06F2221/2129 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/12 ,  H04L2209/26

摘要： A silicon integrated circuit comprises a physically non-copyable function LPUF allowing the generation of a signature specific to said circuit. Said function comprises a ring oscillator composed of a loop traversed by a signal, being formed of N topologically identical chains of lags, connected in series and of an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also comprises a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after the updating of the control words, and means can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided.

摘要翻译： 硅集成电路包括允许产生特定于所述电路的签名的物理上不可复制的功能LPUF。 所述功能包括由信号穿越的环路组成的环形振荡器，由N个拓扑相同的串联链和反向栅极构成，一系列滞后链由串联连接的M个延迟元件组成。 该功能还包括产生N个控制字的控制模块，用于配置由延迟链引入的延迟对穿过它们的信号的值。 测量模块在更新控制字之后测量最后链延迟链输出端的信号频率，并且可以从频率测量中推导构成电路签名的位。 还提供了用于测试这种电路的方法和系统。

公开(公告)号：US20130129081A1

公开(公告)日：2013-05-23

申请号：US13509494

申请日：2010-11-08

申请人： Sylvain Guillet ,  Jean-Luc Danger

发明人： Sylvain Guillet ,  Jean-Luc Danger

IPC分类号： H04L9/28

CPC分类号： H04L9/28 ,  H04L9/003 ,  H04L9/0618 ,  H04L2209/046 ,  H04L2209/12

摘要： A cryptography circuit protected by masking, said circuit including means for encrypting binary words using at least one key krc, means for applying linear processing operations and nonlinear processing operations to said words and means for masking said words. The binary words are unmasked upstream of the nonlinear processing operations by using a mask kri and masked downstream of said processing operations by using a mask kr+1i, the masks kri and kr+1i being chosen from a set of masks that is specific to each instance of the circuit.

摘要翻译： 一种由掩蔽保护的加密电路，所述电路包括用于使用至少一个密钥krc加密二进制字的装置，用于对所述字应用线性处理操作和非线性处理操作的装置以及用于掩蔽所述字的装置。 通过使用掩模kri并通过使用掩模kr + 1i在所述处理操作的下游屏蔽下来的二进制字在非线性处理操作的上游被屏蔽，掩模kri和kr + 1i是从一组特定于每个 电路实例。

公开(公告)号：US5719515A

公开(公告)日：1998-02-17

申请号：US641003

申请日：1996-04-29

申请人： Jean-Luc Danger

发明人： Jean-Luc Danger

IPC分类号： H03K5/14 ,  H03K5/13 ,  H03L7/099 ,  H03K5/159

CPC分类号： H03K5/131 ,  H03K5/133

摘要： A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.

摘要翻译： 数字延迟线从周期性输入信号提供n个信号，该信号具有相互偏移输入信号周期的第n个的相同周期。 数字延迟线包括n个单元，每个单元包括串联的m个延迟元件，延迟元件的每个输出端连接到多路复用器的输入端。 将第n个单元的输出相位与输入信号相位的输出相比较。 每个比较后，n个单元的多路复用器的输出被修改。

公开(公告)号：US20120045061A1

公开(公告)日：2012-02-23

申请号：US13145181

申请日：2010-01-18

申请人： Jean-Luc Danger ,  Sylvain Guilley

发明人： Jean-Luc Danger ,  Sylvain Guilley

IPC分类号： H04L9/14

CPC分类号： H04L9/003 ,  G09C1/00 ,  H04L9/0625 ,  H04L2209/046 ,  H04L2209/12

摘要： A cryptography circuit, protected notably against information-leak observation attacks, comprises a functional key kc for executing a cryptography algorithm. It comprises a second key ki unique and specific to the circuit making it possible to protect by masking the functional and confidential key kc or a confidential implementation of the algorithm.

摘要翻译： 特别是针对信息泄漏观察攻击进行保护的加密电路包括用于执行密码学算法的功能密钥kc。 它包括唯一且特定于电路的第二密钥ki，使得可以通过掩蔽功能和机密密钥kc或算法的机密实现来保护。

公开(公告)号：US07286714B2

公开(公告)日：2007-10-23

申请号：US10251658

申请日：2002-09-19

申请人： Jean-Michel Bard ,  Jean-Luc Danger ,  Lucas Hui ,  Christophe Cunat

发明人： Jean-Michel Bard ,  Jean-Luc Danger ,  Lucas Hui ,  Christophe Cunat

IPC分类号： G06K9/36 ,  G06K9/46

CPC分类号： H04N19/436 ,  H04N19/126 ,  H04N19/152 ,  H04N19/176 ,  H04N19/194 ,  H04N19/196 ,  H04N19/197 ,  H04N19/60

摘要： Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.

摘要翻译： 对数字图像信号进行压缩的方法，其中确定对于给定段是唯一的第一量化步长集合，使得对与该段相对应的量化数据进行编码所需的位数大于目标值。 作为优先级，该第一量化步长作为优先级被修改为在该修改过程中增益对于其对应于该段的量化数据进行编码所需的位数减少的段的块 它属于哪个，是最高的。 在该段的位数小于或等于目标值所需的块上执行该修改。 设备实现这种方法。

公开(公告)号：US08904192B2

公开(公告)日：2014-12-02

申请号：US12933949

申请日：2009-03-18

申请人： Jean-Luc Danger ,  Sylvain Guilley ,  Philippe Hoogvorst

发明人： Jean-Luc Danger ,  Sylvain Guilley ,  Philippe Hoogvorst

IPC分类号： H04L29/06 ,  G06F7/00 ,  G06F21/75 ,  G06F21/55

CPC分类号： G06F7/00 ,  G06F21/75 ,  G06F21/755 ,  G06F2207/7266

摘要： A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.

摘要翻译： 可编程密码学电路包括定义每个单元的逻辑功能的基于存储器的单元，对能够对二进制变量对执行计算的差分网络进行集成，所述差分网络包括在对的第一分量上实现逻辑功能的单元的第一网络，以及 双电池的第二网络在该对的第二部件上以互补逻辑运行。 计算步骤包括预充电阶段，其中变量在单元的输出处被置于已知状态，以及由单元进行计算的评估阶段。 在每个能够接收传送输入变量的信号的每个单元中的评估阶段或预充电阶段之前插入使变量同步的阶段，同步是在最延迟的信号上执行的。

公开(公告)号：US20120124680A1

公开(公告)日：2012-05-17

申请号：US13058706

申请日：2009-07-30

申请人： Jean-Luc Danger ,  Sylvain Guilley ,  Florent Flament

发明人： Jean-Luc Danger ,  Sylvain Guilley ,  Florent Flament

IPC分类号： G06F21/00

CPC分类号： G06F21/558 ,  G06F21/75 ,  G06F21/755

摘要： In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.

摘要翻译： 在用于检测由差分逻辑保护并且处理由一对分量表示的逻辑变量的电路中的异常的方法中，第一网络单元在所述对的第一分量上执行逻辑功能，第二双电池网络在 在第二组件上的互补逻辑，逻辑功能由预充电阶段中的每对单元执行，将变量置于已知状态，并输入到单元中，随后是由单元执行计算的评估阶段 该方法包括通过至少一个不一致状态来检测异常。