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    Via selection in integrated circuit design
    1.
    发明授权
    Via selection in integrated circuit design 有权
    通过集成电路设计中的选择

    公开(公告)号：US08631375B2

    公开(公告)日：2014-01-14

    申请号：US13443426

    申请日：2012-04-10

    申请人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

    发明人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

    摘要翻译： 公开了将通孔有效地实现为多级集成电路布局的解决方案。 在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益 多个通孔。

    METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF
    2.
    发明申请
    METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF 有权
    在逻辑设计中管理电迁移的方法及其设计结构

    公开(公告)号：US20110173583A1

    公开(公告)日：2011-07-14

    申请号：US12686457

    申请日：2010-01-13

    申请人： John E. BARWIN ,  Jeanne P. S. BICKFORD

    发明人： John E. BARWIN ,  Jeanne P. S. BICKFORD

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

    摘要翻译： 设计集成电路的方法包括基于至少一个可靠性约束来修改每个预定义电路的设计属性可变电迁移（EM）极限，以避免EM集成电路的违规。 该方法还包括使用每个预定义电路的经修改的设计变量EM限制将集成电路从高级描述合成到至少一个预定义电路装置的子集。

    Integration of business process and use of fields in a master database
    3.
    发明授权
    Integration of business process and use of fields in a master database 有权
    集成业务流程和在主数据库中使用字段

    公开(公告)号：US07386549B2

    公开(公告)日：2008-06-10

    申请号：US10249690

    申请日：2003-04-30

    申请人： Jeanne P. S. Bickford ,  Ernest J. Burger ,  Thomas R. Maheux ,  Paul G. McLaughlin

    发明人： Jeanne P. S. Bickford ,  Ernest J. Burger ,  Thomas R. Maheux ,  Paul G. McLaughlin

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30368 ,  Y10S707/99938

    摘要： A system that registers the relationship of use and dependencies in a master source database (i.e., a registration schema) thereby providing cohesiveness between the master source data and downstream systems that receive the master source data fields. The registration schema provides rules for a generic data bridge which executes the movement of master source database data to downstream systems, providing further cohesive connection between what was registered for use and dependencies and what actually occurs in the movement of data to downstream systems. The generic data bridge's actions, on a field-by-field basis, are documented in a use and dependency model. In addition, modification of the use and dependencies registration section of the master source database allows changes to made as opposed to having to modify specific system bridges.

    摘要翻译： 在主源数据库（即注册模式）中注册使用和依赖关系的系统，从而提供主源数据和接收主源数据字段的下游系统之间的内聚性。 注册模式为通用数据桥提供规则，该通用数据桥执行主源数据库数据向下游系统的移动，从而在注册使用和依赖关系之间提供进一步的内聚连接以及数据向下游系统移动的实际情况。 通用数据桥的操作在逐个字段的基础上被记录在使用和依赖关系模型中。 此外，主源数据库的使用和依赖注册部分的修改允许进行更改，而不必修改特定的系统网桥。

    Method of managing electro migration in logic designs and design structure thereof
    4.
    发明授权
    Method of managing electro migration in logic designs and design structure thereof 有权
    在逻辑设计及其设计结构中管理电迁移的方法

    公开(公告)号：US08560990B2

    公开(公告)日：2013-10-15

    申请号：US12686457

    申请日：2010-01-13

    申请人： John E. Barwin ,  Jeanne P. S. Bickford

    发明人： John E. Barwin ,  Jeanne P. S. Bickford

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

    摘要翻译： 设计集成电路的方法包括基于至少一个可靠性约束来修改每个预定义电路的设计属性可变电迁移（EM）极限，以避免EM集成电路的违规。 该方法还包括使用每个预定义电路的经修改的设计变量EM限制将集成电路从高级描述合成到至少一个预定义电路装置的子集。

    VIA SELECTION IN INTEGRATED CIRCUIT DESIGN
    5.
    发明申请
    VIA SELECTION IN INTEGRATED CIRCUIT DESIGN 有权
    通过集成电路设计中的选择

    公开(公告)号：US20130268908A1

    公开(公告)日：2013-10-10

    申请号：US13443426

    申请日：2012-04-10

    申请人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

    发明人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

    摘要翻译： 公开了将通孔有效地实现为多级集成电路布局的解决方案。 在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益 多个通孔。